Win-San Khwa, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang, "Shift register having low power mode," US-20250316321-A1, Oct. 9, 2025 (TSMC)
Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang, "Memory test circuit, memory chip, and testing method of memory chip," US-20250316323-A1, Oct. 9, 2025 (TSMC)
Win-San Khwa, Jui-Jen Wu, Jen-Chieh Liu, Meng-Fan Chang, "Memory devices, circuits and methods of adjusting a sensing current for the memory device," US-20250299716-A1, September 25, 2025 (TSMC)
Win-San Khwa, Jui Jen Wu, Jen-Chieh Liu, Meng-Fan Chang, "Non-volatile memory stored with encoded data," US-20250292830-A1, September 18, 2025 (TSMC)
Win-San Khwa, Hung-Hsi Hsu, Jui-Jen Wu, Meng-Fan Chang, "System, memory device and method," US-20250285701-A1, September 11, 2025 (TSMC)
Win-San Khwa, De-Qi You, Jui-Jen Wu, Meng-Fan Chang, "Memory device and operating method thereof," US-20250252995-A1, August 7, 2025 (TSMC)
Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Meng-Fan Chang, "System, circuit and method for data processing," US-20250251909-A1, August 7, 2025 (TSMC)
Win-San Khwa, De-Qi You, Jui-Jen Wu, Meng-Fan Chang, "Memory device and operating method thereof," US-20250253005-A1, August 7, 2025 (TSMC)
Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang, "Device having rows of mram cells configured for concurrent writing and reading," US-20250239285-A1, July 24, 2025 (TSMC)
Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang, "Cross-point memory cell and method," US-20250240976-A1, July 24, 2025 (TSMC)
Jui-Jen Wu, Ping-Chun Wu, Win-San Khwa, Meng-Fan Chang, "Storage circuit, self-refresh unit and memory array," US-20250239289-A1, July 24, 2025 (TSMC)
Win-San Khwa, Hung-Hsi Hsu, Xiaochen Peng, Murat Kerem Akarvardar, Meng-Fan Chang, "Mantissa alignment," US-20250224922-A1, July 10, 2025 (TSMC)
Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang, "Method for controlling sense amplifier and control device using the same," US-20250218474-A1, July 3, 2025 (TSMC)
Ashwin Sanjay Lele, Win-San Khwa, Meng-Fan Chang, "Storage device having latching units serially connected for in-memory arithmetic operations," US-20250219620-A1, July 3, 2025 (TSMC)
Win-San Khwa, Jui-Jen Wu, Jen-Chieh Liu, Meng-Fan Chang, "Memory devices, circuits and methods of adjusting a sensing current for the memory device," US-12347474-B2, July 1, 2025 (TSMC)
Win-San Khwa, Jui Jen Wu, Jen-Chieh Liu, Meng-Fan Chang, "Non-volatile memory stored with encoded data," US-12334151-B2, June 17, 2025 (TSMC)
Win-San Khwa, Meng-Fan Chang, "Sensing amplifier of memory array, memory device and data read method with two state reference voltages," US-12562203-B2, May 22, 2025 (TSMC)
Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang, "Method for controlling sense amplifier and control device using the same," US-12283340-B2, April 22, 2025 (TSMC)
Tai-Hao Wen, Meng-Fan Chang, Win-San Khwa, "Memory system and operating method of the same," US-12475935-B2, Aug. 22, 2024 (TSMC)
Hung-Li Chiang, Jer-Fu Wang, Chen Tzu-Chiang, Meng-Fan Chang,"Memory device, method for configuring memory cell in N-bit memory unit, and memory array," US-US12069970-B2, Aug. 20, 2024 (TSMC)
Win-San Khwa, Jui Jen Wu, Jen-Chieh Liu, Meng-Fan Chang,"Method of data encoding in non-volatile memories," US-12057164-B2, Aug. 6, 2024 (TSMC)
Win-San Khwa, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang, "Shift register having low power mode," US-12362027-B2, Aug. 1, 2024 (TSMC)
Jen-Chieh Liu, Jui-Jen Wu, Win-San Khwa, Yi-Lun Lu, Meng-Fan Chang,"High-density memory cells and layouts thereof," US-12051457-B2, July 30, 2024 (TSMC)
Win-San Khwa, Yen-Cheng Chiu, Je-Min Hung, Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang,"Memory device with low power consumption and operation method thereof," US-12040011-B2, July 16, 2024 (TSMC)
Jui-Jen Wu, Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang, "Sense amplifier circuit and method," US-12354701-B2, July 11, 2024 (TSMC)
CHIU Yen-Cheng, Win-San Khwa, Meng-Fan Chang,"Memory device and operating method thereof," US-12033697-B2, July 9, 2024 (TSMC)(NTHU)
Win-San Khwa, Jui-Jen Wu, Jen-Chieh Liu, Meng-Fan Chang,"Method of storing data in memories," US-12009051-B2, June 11, 2024 (TSMC)
Yu-Der Chih, Meng-Fan Chang, May-Be Chen, Cheng-Xin Xue, Je-Syu Liu,"System and method applied with computing-in-memory," US-12009029-B2, June 11, 2024 (TSMC)
Meng-Fan Chang, Yen-Chi Chou, Jian-Wei Su,"Memory device and memory array structure using charge sharing for multi-bit convolutional neural network based computing-in-memory applications, and computing method thereof," US-12002539-B2, June 4, 2024 (NTHU)
Meng-Fan Chang, Chiu Yen-Cheng,"Memory and operating method thereof," US-11996147-B2, May 28, 2024 (TSMC) (NTHU)
Win-San Khwa,Yi-Lun Lu, Jui-Jen Wu, Meng-Fan Chang,"Shift register having low power mode," US-11990194-B2, May 21, 2024 (TSMC)
Meng-Fan Chang, Ping-Chun Wu, Li-Yang Hong, Jin-Sheng Ren, Jian-Wei Su,"Memory unit with time domain edge delay accumulation for computing-in-memory applications and computing method thereof," US-11967357-B2, April 23, 2024 (NTHU)
Jui-Jen Wu, Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang,"Sense amplifier circuit and method," US-11942178-B2, March 26, 2024 (TSMC)
Je-Min Hung, Win-San Khwa, Meng-Fan Chang,"Memory device and method," US-11942185-B2, March 26, 2024 (TSMC)
Jer-Fu Wang, Hung-Li Chiang, Yi-Tse Hung, Tzu-Chiang chen, Meng-Fan Chang,"Memory device with sram cells assisted by non-volatile memory cells and operation method thereof," US-11929115-B2, March 12, 2024(TSMC)
Jui-Jen Wu, Jen-Chieh Liu, Yi-Lun Lu, Win-San Khwa, Meng-Fan Chang, "Memory test circuit, memory chip, and testing method of memory chip," US-12362028-B2, March 7, 2024 (TSMC)
Win-San Khwa, Jui-Jen Wu, Jen-Chieh Liu, Meng-Fan Chang,"Memory devices, circuits and methods of adjusting a sensing current for the memory device," US-11915733-B2, Feb. 27, 2024 (TSMC)
Kerem Akarvardar, Win-San Khwa, Rawan Naous, Jin Cai, Meng-Fan Chang, Hon-Sum Philip Wong,"Memory array, memory structure and operation method of memory array," US-11901004-B2, Feb. 13, 2024 (TSMC)
Hung-Li
Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang, “Data
processing method, data processing circuit, and computing apparatus,” US-11854594, Dec 26, 2023
(TSMC)
Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang, Tung-Ying Lee, Jin Cai, "Control circuit, memory system and control method," US-12424298-B2, Nov. 9, 2023 (TSMC)
Meng-Fan
Chang, Wei-Hsing Huang, Ta-Wei Liu, “Dynamic gradient calibration method
for computing-in-memory neural network and system thereof”, US-11763162, Sept 19, 2023
(NTHU)
Win-San Khwa, Jen-Chieh Liu, Meng-Fan
Chang, Tung-Ying Lee, Jin Cai,
“Control circuit, memory system and control method,” US-11756645-B2, Sept, 12, 2023 (TSMC)
Yen-Cheng Chiu, Win-San Khwa, Meng-Fan Chang, "Systems and methods for reading bit state in arrays of memory cells," US-12469537-B2, Sep. 7, 2023 (TSMC)
Meng-Fan Chang, Ping-Chun Wu, Jin-Sheng Ren, Li-Yang Hong, Ho-Yu Chen, "Memory array structure with dynamic differential-reference based readout scheme for computing-in-memory applications, dynamic differential-reference time-to-digital converter for computing-in-memory applications and computing method thereof," US-12386592-B2, August 17, 2023 (TSMC)
Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang, "3T memory with enhanced speed of operation and data retention," US-12396176-B2, July 27, 2023 (TSMC)
Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang, "Memory devices and methods of forming the same," US-12402327-B2, July 13, 2023 (TSMC)
Hung-Li Chiang, Jer-Fu Wang, Tzu-Chiang Chen, Meng-Fan Chang, "Self-aligned contact for embedded memory," US-12424492-B2, June 22, 2023 (TSMC)
Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang,
“Selector-based random number generator and method thereof,”
US-11664790-B2, May 30, 2023 (TSMC)
Yu-Der
Chih, Meng-Fan Chang, May-be Chen, Cheng-Xin Xue, Je-Syu Liu,
“System and method applied with computing-in-memory”, US-11621040-B2,
April 04, 2023 (TSMC)
Fu-Chun
Chang, Ta-Wei Liu, Cheng-Xin Xue, Sheng-Po Huang, Yen-Hsiang Huang,
Meng-Fan Chang, “Input-shaping method and input-shaping unit for
group-modulated input scheme in computing-in-memory applications”,
US-11621723-B2, April 04, 2023 (NTHU)
Yen-Cheng Chiu, Ta-Wei Liu, Fu-Chun Chang, Meng-Fan Chang, "Input sequence re-ordering method and input sequence re-ordering unit with multi input-precision reconfigurable scheme and pipeline scheme for computing-in-memory macro in convolutional neural network application," US-12423059-B2, Dec. 08, 2022 (TSMC)
Meng-Fan
Chang and Pei-Jung Lu, “Memory unit with multi-bit input local computing
cell for multi-bit convolutional neural network based computing-in-memory
applications, memory array structure with multi-bit input local computing cell
for multi-bit convolutional neural network based computing-in-memory
applications and computing method thereof,” U.S. Patent 11507275,
Nov 22, 2022 (NTHU)
Meng-Fan Chang, Jan-Wen Hu, Kuang-Tang Chang, “Memory unit with
multiply-accumulate assist scheme for multi-bit convolutional neural network
based computing-in-memory applications and computing method thereof,” U.S.
Patent 11500613, Nov. 15, 2022 (NTHU)
Meng-Fan Chang, Yung-Ning
Tu, Wei-Hsing Huang, “Memory unit for multi-bit convolutional neural
network based computing-in-memory applications, memory array structure for
multi-bit convolutional neural network based computing-in-memory
applications and computing method,” U.S. Patent 11495287, Nov 08, 2022 (NTHU)
Meng-Fan Chang, Jing-Hung Wang,
Ta-Wei Liu, “Quantization method for partial sums of convolution neural network
based on computing-in-memory hardware and system thereof,” U.S. Patent 11423315,
Aug 23, 2022 (NTHU)
Meng-Fan Chang, Jian-Wei Su,
Je-Ming Hung, Chuang-Jia Jhang, Ping-Chun Wu, Jin-Sheng Ren, “Memory structure
with input-aware maximum multiply-and-accumulate value zone prediction for
computing-in-memory applications and operating method thereof “ U.S. Patent 11416146, Aug. 16, 2022 (NTHU)
Cheng-Xin Xue, Hui-Yao Kao,
Sheng-Po Huang, Yen-Hsiang Huang, Meng-Fan Chang “Transpose memory unit for
multi-bit convolutional neural network based computing-in-memory applications,
transpose memory array structure for multi-bit convolutional neural network
based computing-in-memory applications and computing method thereof,” U.S.
Patent 11393523,
July 19, 2022 (NTHU)
Win-San Khwa,
Jui-Jen Wu, Jen-Chieh Liu, Elia Ambrosi, Xinyu Bao, Meng-Fan Chang,
“Selector-based random number generator and method thereof,” U.S. Patent
11,349,462, May 31, 2022 (TSMC)
Yen-Hsiang Huang,
Sheng-Po Huang, Cheng-Xin Xue, Meng-Fan Chang, “Memory unit with
multiple word lines for nonvolatile computing-in-memory applications and
current calibrating method thereof,” U.S. Patent 11,335,401, May 17, 2022
(NTHU)
Meng-Fan Chang, Cheng-Xin Xue,
Je-Syu Liu, Ting-Wei Chang, Tsung-Yuan Huang;, Hui-Yao Kao,“Memory unit with adaptive clamping
voltage scheme and calibration scheme for multi-level neural network based
computing-in-memory applications and computing method thereof,” U.S.
Patent 11,195,090, Dec. 7, 2021 (NTHU)
Meng-Fan Chang, “Method and system
for performing physical unclonable function generated by non-volatile
memory write delay difference,” U.S. Patent 11,057,224, July 6, 2021
(NTHU)
Tung-Cheng Chang,
Chun-Ying Lee, Meng-Fan Chang, “Multi-bit current sense amplifier
with pipeline current sampling of resistive memory array structure and
sensing method thereof,” U.S. Patent 11,049,550, June 29, 2021 (NTHU)
Kea-Tiong Tang,
Meng-Fan Chang, Chih-Cheng Hsieh, Syuan-Hao Sie, “Method and system
for integrating processing-in-sensor unit and in-memory computing unit,”
U.S. Patent 11,048,650, June 29, 2021 (NTHU)
Wei-Yu Lin,Meng-FanChang, “Sensing circuit with adaptive local reference generation of
resistive memory and sensing method thereof”, U.S. Patent 10,748,612, Aug.
18, 2020 (NTHU)
Meng-Fan
Chang,
Huan-Ting Lin,“Voltage-enhanced-feedback
sense amplifier of resistive memory and operating method thereof” U.S.
Patent 10,734,039, Aug. 4, 2020 (NTHU)
Meng-Fan Chang, Xin Si, Yung-Ning
Tu, Jia-Jing Chen, “Memory cell for computing-in-memory applications,
memory unit for computing-in-memory applications and computing method
thereof,” U.S. Patent 10,636,481, April 28, 2020 (NTHU)
Meng-Fan Chang, Wen-Zhang Lin,
Li-Ya Lai, “Control circuit configured to terminate a set operation and a
reset operation of a resistive memory cell of memory array based on the
voltage variation on the data line of the resistive memory cell,” U.S.
Patent 10,607,698, March 31, 2020 (NTHU)
Meng-Fan Chang, Huan-Ting Lin,
Tsung-Yuan Huang, Wei-Hao Chen, Han-Wen Hu, “Soft-verify write assist
circuit of resistive memory and operating method thereof,” U.S. Patent
10,510,406, Dec. 17, 2019 (NTHU)
Meng-Fan Chang, Wei-Hao Chen,
Wei-Yu Lin, “Dynamic bit-line clamping circuit for computing-in-memory
applications and clamping method thereof,” U.S. Patent 10,510,386, Dec.
17, 2019 (NTHU)
Meng-Fan Chang, Huan-Ting Lin,
Tsung-Yuan Huang, Wei-Hao Chen, Han-Wen Hu, “Reference-free multi-level
sensing circuit for computing-in-memoryapplications, reference-free memory
unit for computing-in-memory applications and sensing method thereof,”
U.S. Patent 10,410,690, Sept. 10, 2019 (NTHU)
Xin Si, Meng-Fan
Chang, “Multi-bit computing circuit for computing-in-memory
applications and computing method thereof,” U.S. Patent 10,381,071, August
13, 2019 (NTHU)
Meng-Fan Chang, Wei-Hao Chen,
“Input-pattern aware reference generation system and
computing-in-memorysystem including the same”, U.S. Patent 10,340,003,
July 2, 2019 (NTHU)
Meng-Fan Chang, “Transpose accessing memory
device and method”, U.S. Patent 10,262,726 , April 16, 2019 (NTHU)
Meng-Fan Chang, Win-San Khwa, Jia-Jing Chen,
“Selective bit-line sensing method and storage device utilizing the same”,
U.S. Patent10,262,725, April 16, 2019 (NTHU)
Meng-Fan Chang, Win-San Khwa, Jia-Jing Chen,
“Method and circuit for generating a reference voltage in neuromorphic
system”, U.S. Patent10,249,360, April 2, 2019 (NTHU)
Meng-Fan Chang, Wen-Zhang Lin, Li-Ya Lai,
“Control circuit configured to terminate a set operation and a reset
operation of a resistive memory cell of memory array based on the voltage
variation on the data line of the resistive memory cell”, U.S. Patent10,204,681,
Feb. 12, 2019 (NTHU)
Tzu-Hsien Yang, Meng-Fan Chang, “Sensing circuit,
set of pre-amplifiers, and operating method thereof”, U.S. Patent10,192,611,
Jan. 29, 2019 (NTHU)
Tzu-Hsien Yang,
Meng-Fan Chang, “Sense amplifier of resistive memory and operating method
thereof”, U.S. Patent10,186,318, Jan. 22, 2019 (NTHU)
Win-San Khwa, Meng-Fan Chang, Jen-Chien Fu,
Shuai-Fan Chen, ”Control method for solid state storage device, U.S.
Patent10,008,275, June 26, 2018 (Lite-on)
Tien-Fu
Chen, Meng-Fan Chang, Keng-Hao Yang, “Tag
memory and cache system with automating tag comparison mechanism and cache
method thereof,”U.S. Patent9,990,302, June 5,
2018 (NCTU)
Meng-Fan Chang, Yi-Ju Chen, ” Memory
apparatus and write failure responsive negative bitline voltage write
assist circuit thereof,” U.S. Patent9,779,802, Oct. 3,
2017 (NTHU)
Meng-Fan Chang, Wei-Chang Zhao, ”Ternary
content addressable memory,” U.S. Patent9,728,258, Aug. 8,
2017 (NTHU)
Meng-Fan Chang, Albert Lee, Chieh-Pu Lo,
Chien-Chen Lin “Non-volatile latch,” U.S. Patent9,722,584,
Aug. 1, 2017 (NTHU)
Meng-Fan Chang, Chien-Fu Chen, Hiroyuki
Yamauchi, “6T static random access memory cell, array and memory thereof,”
U.S. Patent9,627,040, April 18, 2017 (NTHU)
Albert Lee,
Chien-Chen Lin, Chieh-Pu Lo, Meng-Fan
Chnag, “Non-volatile static random access memory using a 7T1R cell
with initialization and pulse overwrite,” U.S. Patent9,564,209,
Feb. 7, 2017 (NTHU)
Win-San Khwa;, Tzu-Hsiang Su, Chao-I Wu, Hsiang-Pan Li, Meng-FanChang, “Resistance drift
recovery method for MLC PCM,” U.S. Patent9,558,823, Jan. 31,
2017 (MXIC)
Yih-Shan Yang,
Shou-Nan Hung, Chun-Hsiung Hung, Yao-Jen Kuo, Meng-Fan Chang, “Method and apparatus for determining status
element total with sequentially coupled counting status circuits,” U.S.
Patent9,548,135, Jan. 17, 2017 (MXIC)
Chien-Chen Lin,
Albert Lee, Chieh-Pu Lo, Meng-Fan
Chang, “Non-volatile ternary content-addressable memory with
bi-directional voltage divider control and multi-step search,” U.S.
Patent9,502,114, Nov. 22, 2016 (NTHU)
Pei-Ling Tseng, Chia-ChenKuo,
Shyh-ShyuanSheu, Meng-FanChang,”Resistive memory system, driver circuit thereof and method
for setting resistance thereof,” ” U.S. Patent9,443,588,
Sept. 13, 2016 (ITRI)
Meng-Fan Chang,Yu-LinChen, Chia-YinLi,
Tien-FuChen, Keng-Hao Yang,
”Memory apparatus,” U.S. Patent9,431,070, Aug. 30,
2016 (NTHU)
Meng-Fan Chang,
Yu-LinChen, ” Sense Amplifier,”U.S. Patent9,406,355, Aug. 2, 2016
(NTHU)
Meng-Fan Chang, Jui-Yu Hung, "Sense
Amplifier,” U.S. Patent9,378,780,
June 28, 2016 (NTHU)
Meng-Fan Chang, Tsung-Hsien Huang, Pei-Yuan
Li, “Scheme for 3D voltage type TSV signal transmission,” U.S. Patent9,312,856, April 12, 2016 (NTHU)
Meng-Fan Chang, Ching-HaoChuang,
“Non-volatile ternary content-addressable memory with resistive memory
device” U.S. Patent9,312,006,
April 12, 2016 (NTHU)
Chien-Fu Chen, Meng-Fan Chang, HiroyukiYamauchi,
Yen-Yao Wang, "6T static random access memory
cell, array and memory thereof,” U.S. Patent9,299,422, March 29, 2016 (NTHU)
Meng-Fan Chang, Li-Yue Huang, "Non-volatile
ternary content-addressable memory 4T2R cell with RC-delay search,” U.S.
Patent9,230,649, Jan. 5, 2016
(NTHU)
Meng-Fan Chang, Jui-JenWu, Yen-Chen Liu, "Sensing
margin expanding scheme for memory,” U.S. Patent9,171,590, Oct. 27, 2015 (NTHU)
Meng-Fan Chang, Tsung-Hsien Huang, "3D-IC
differential sensing and charge sharing scheme,” U.S. Patent9,170,287, Oct. 27, 2015 (NTHU)
Meng-Fan
Chang,
Wei-Cheng Wu, Tsung-Hsien Huang, Chien-Yuan Chen, "Control scheme for 3D
memory IC,” U.S. Patent9,013,908, April
21, 2015 (NTHU)
Meng-Fan
Chang,
Chien-Fu Chen, Ting-Hao Chang, Hiroyuki Yamauchi, “6T static random access
memory cell, array and memory thereof,” U.S. Patent9,001,571 , April 7, 2015. (NTHU)
Ching-Hao Chuang, Meng-Fan Chang, Shyh-Shyuan Sheu,
Zhe-Hui Lin, “Memory storage circuit and method of driving memory storage
circuit,” U.S. Patent 8,942,027, Jan. 27, 2015. (ITRI)
Jui-Jen Wu, Tun-Fei Chien, Meng-Fan Chang, Yu-Der Chih, “Sensing amplifier using capacitive coupling
to realize dynamic reference voltage” U.S. Patent 8,854,083, Oct. 7, 2014.
(NTHU)
Jui-Jen Wu, Meng-Fan Chang,
“Sensing memory element logic states from bit line discharge rate that varies
with resistance” US 8,848,419, Sept. 30, 2014. (TSMC)
Ming-Pin Chen, Meng-Fan Chang,
Wei-Cheng Wu, “Pulse type layer-ID detector for 3D-IC and method of the same,”
U.S. Patent 8,829,887, Sept. 9, 2014. (NTHU)
Ming-Pin Chen, Meng-Fan Chang,
“Layer-ID detector for multilayer 3D-IC and method of the same,” U.S. Patent
8,680,909, March 25, 2014. (NTHU)
Ming-Pin Chen, Meng-Fan Chang,
Wei-Cheng Wu, “Discontinuous type layer-ID detector for 3D-IC and method of the
same,” U.S. Patent 8,564,305, Oct. 22, 2013. (NTHU)
Meng-Fan Chang, Yu-Fan Lin, Shin-Jang
Shen, Yu-Der Chih, “Low-offset current-sense amplifier and operating method
thereof,” U.S. Patent 8,497,710, July 30, 2013. (NTHU)
Meng-Fan Chang, Lai-Fu Chen, Jui-Jen
Wu, Hiroyuki Yamauchi, “Static random access memory cell,” U.S. Patent
8,462,540, June 11, 2013. (NTHU)
Ku-Feng Lin, Meng-Fan Chang,
Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin, Chih-He Lin, “Process variation
detection apparatus and process variation detection method,” U.S. Patent
8,392,132, March 5, 2013. (ITRI)
Meng-Fan Chang, Shin-Jang Shen, Yi-Lun
Lu, “Charge pump system for low-supply voltage,” U.S. Patent 8,390,365, March
5, 2013. (NTHU)
Che-Wei Wu, Meng-Fan Chang,
Ku-Feng Lin, “Bulk-driven current-sense amplifier and operating method
thereof,” U.S. Patent 8,378,716, Feb. 19, 2013. (NTHU)
Pi-Feng Chiu; Meng-Fan Chang,
Ku-Feng Lin, Shyh-Shyuan Sheu,” Non-volatile static random access memory and
operation method thereof,” U.S. Patent 8,331,134, Dec. 11, 2012. (ITRI)
Meng-Fan Chang, Yu-Fan Lin, Shin-Jang
Shen, Yu-Der Chih, “Current-sense amplifier with low-offset adjustment and
method of low-offset adjustment thereof,” U.S. Patent 8,320,211, Nov. 27,
2012. (NTHU)
Meng-Fan Chang, Shin-Jang Shen,
Wan-Ying Lu, “Charge pump with low noise and high output current and voltage,”
U.S. Patent 8,274,322, Sept. 25, 2012. (NTHU)
Meng-Fan Chang, Ku-Feng Lin, Pi-Feng
Chiu, “Reference current generator for resistance type memory and method
thereof,” U.S. Patent 8,213,213, July 3, 2012. (NTHU)
Meng-Fan Chang, Shin-Jang Shen, and
Chia-Chi Liu, “Offset cancellation current mirror and operating method
thereof,” U.S. Patent 8,169,255, May 1, 2012. (NTHU)
Chia-Chi Liu, Shin-Jang Shen, and Meng-Fan
Chang, “Current sensing amplifier and method thereof,” U.S. Patent
8,072,244, Dec. 6, 2011. (NTHU)
Meng-Fan Chang, Chih-Wen Cheng,
“Memory refresh system and operating method thereof,” U.S. Patent 8,009,498,
Aug. 30, 2011. (NTHU)
Wei-Cheng Wu, Yen-Huei Chen, Meng-Fan
Chang, et al., “Differential sensing and TSV timing control scheme for
3D-IC,” U.S. Patent No. 7,969,193, June 28, 2011. (NTHU)
Meng-Fan Chang, “Dual mode accessing
signal control apparatus and dual mode timing signal generating apparatus,”
U.S. Patent No. 7,839,706, Nov. 23, 2010. (NTHU)
Meng-Fan Chang, Shu-Meng Yang and
Jiunn-Way Miaw, “Single-ended sense amplifier using dynamic reference voltage
and operation method thereof,” U.S. Patent No. 7,768,321 August 3, 2010. (ITRI)
Meng-Fan Chang, “Access unit for a
static random access memory,” U.S. Patent No. 7,710,815 May 4, 2010. (NTHU)
Meng-Fan Chang, “Skew free control of
a multi-block SRAM,” U.S. Patent No. 7,356,656, April 8, 2008. (TSMC)
Meng-Fan Chang and K.-A. Wen,
“Method for eliminating crosstalk in a metal programmable read only memory,”
U.S. Patent No. 7289376, Oct. 30, 2007 (NCTU)
Chang Meng Fan (Meng-Fan Chang), “Bit line tracking
scheme with cell current variation and substrate noise consideration for SRAM
devices”, U.S. Patent No. 6731534, May 4, 2004 (TSMC)
Nai-Yin Sung, Tsung-Yi Wu, Meng-Fan
Chang, and Hsien-Te Chen, “System and measuring access time of embedded
memories,” U.S. Patent No. 6424583, July 23, 2002 (TSMC)
Meng-Fan Chang, “Dummy memory cells
for high accuracy self-timing circuits in dual-port SRAM,” U.S. Patent No.
6285604, Sept. 4, 2001 (TSMC)