Publications

Journal Papers

Conference Papers

Patents

Book Chapters and others

Highlights (updated on Feb 2026)

l 120+ top conference papers: ISSCC (52), VLSI Symp. (36), IEDM (26), DAC (7)

Conference Papers (研討會論文)

1. Jen-Chun Tien, Win-San Khwa, Le-Jung Hsieh, Tsung-Han Lou, Jyun-Cheng Bai, Yu-Sheng Kao, Ting-Hao Hsu, Mai Tseng, Hung-Hsi Hsu, Yao-Kai Yeh, De-Qi You, Ashwin Sanjay Lele, Brian Crafton, Bo Zhang, Ping-Sheng Wu, Ya-Tang Yang, Chung-Chuan Lo, Ren Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 16nm 72Kb 120.5TFLOPS/W Versatile-Format Dual-Representation Gain-Cell CIM Macro for General Purpose AI Tasks,” 2026 IEEE International Solid-State Circuits Conference (ISSCC), (Accepted)

2. Yao-Kai Yeh, Jian-Wei Su, Ting-Hao Hsu, Mai Tseng, Jen-Chun Tien, Ko-Chi Chen, Chih-Yen Yue, Yu-En Lin, Yu-Jia Hu, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Hung-Hsi Hsu, De-Qi You, Sheu Shyh-Shyuan, Wei-Chung Lo, Shih-Chieh Chang, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 16nm 1Mb, 1-8b-Configurable 444.21TOPS/W Fully-Digital SRAM Compute-In-Memory Macro for Hybrid SNN-CNN Edge Computing,” 2026 IEEE International Solid-State Circuits Conference (ISSCC), (Accepted)

3. Hung-Hsi Hsu, Win-San Khwa, Yao-Kai Yeh, Chih-Ling Wu, Chang-Yuan Chen, Yen-Che Huang, Yen-Hua Lin, Cheng-Feng Chang, Yen-Tung Shao, Jen-Chun Tien, De-Qi You, Ping-Sheng Wu, Bo Zhang, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 22nm 96Mb 50.6-90.2TFLOPS/W Non-Linear MLC ReRAM CIM Macro with High-Retention for Mamba/Transformer/CNN,” 2026 IEEE International Solid-State Circuits Conference (ISSCC), (Accepted)

4. Shuhan Liu, Koustav Jana, Leo Jen-Chieh Liu, Elia Ambrosi, Mingyuan Song, Louis Liu, Jing Wang, Subhasish Mitra, Xin-Yu Bao, Meng-Fan Chang, John R. Hu, John Y. Chen, Jian Chen, H.-S. Philip Wong, "Amp Cell: 3D-Scalable Gain Cell Memory with Decoupled Read, Write, and Store," 2025 IEEE International Electron Devices Meeting (IEDM), pp. 1-4, San Francisco, CA, USA, Dec. 2025, (Accepted)

5. Carlo Gilardi, Goutham Arutchelvan, Xiaoyu Sun, Chih-Yu Chang, Jen-Chieh Liu, Aslan Wei, D. Mahaveer Sathaiya, Jui Jen Wui, Win-San Khwa, Meng-Fan Chang, Katherine H. Chiang, Kerem Akarvardar, Iuliana Radu, Min Cao, “COMET: Co-Optimization of Memory with Exploratory Technologies for Hybrid and Back-End Gain Cell Arrays,” 2025 IEEE International Electron Devices Meeting (IEDM), pp. 1-4, San Francisco, CA, USA, Dec. 2025, (Accepted)

6. Junmo Lee, Chengyang Zhang, Siheon Park, Hyeonwoo Park, Tae-Hyeon Kim, Leo Jen-Chieh Liu, Elia Ambrosi, Mingyuan Song, Xin-Yu Bao, Meng-Fan Chang, Suman Datta, Shimeng Yu, “Monolithic 3D Integration of Dual-Gated ALD Oxide-Channel Non-Volatile Capacitive Memory on 40nm Si CMOS for Digital Compute-in-Memory,” 2025 IEEE International Electron Devices Meeting (IEDM), pp. 1-4, San Francisco, CA, USA, Dec. 2025, (Accepted)

7. Shuhan Liu, Koustav Jana, Louis Liu, Jing Wang, Leo Jen-Chieh Liu, Elia Ambrosi, Mingyuan Song, Christian Kubicka, Yiming Tan, Haitong Li, Subhasish Mitra, Jian Chen, Thierry Tambe, Xin-Yu Bao, Meng-Fan Chang, John R. Hu, John Y. Chen, H.-S. Philip Wong , “Gain Cell Memory Scalability to 5-nm and Beyond,” 2025 IEEE International Electron Devices Meeting (IEDM), pp. 1-4, San Francisco, CA, USA, Dec. 2025, (Accepted)

8. Chang Eun Song, Weihong Xu, Keming Fan, Soumil Jain, Gopabandhu Hota, Haichao Yang, Leo Liu, Meng-Fan Chang, Carlos H. Diaz, Gert Cauwenberghs, Tajana Rosing, and Mingu Kang,"Clo-HDnn: Continual On-Device Learning Accelerator with Hyperdimensional Computing via Progressive Search," 2025 IEEE Hot Chips, CA, USA, Aug. 2025.

9. Hung-Hsi Hsu, Win-San Khwa, Tai-Hao Wen, Wei-Ting Hsu, Yu-Chen Chang, Hsin-Yin Lu, Hua-Jin Wen, Chang-Yuan Chen, Yen-Che Huang, Chih-Ling Wu, Ping-Sheng Wu, Mon-Shu Ho, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tan , Shih-Hsin Teng, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*,"A 22nm 41.8TFLOPS/W AI-Edge Transformer/CNN Nonvolatile-Processor Using QKV-Softmax-Layer-Fused Hybrid ReRAM-CIM and Concurrent-Transpose/Non-Transpose SRAM-CIM," 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), C17-2, Kyoto, Japan, Jun. 2025.

10. Chang Eun Song, Weihong Xu, Keming Fan, Soumil Jain, Gopabandhu Hota, Haichao Yang, Leo Liu, Kerem Akarvardar, Meng-Fan Chang, Carlos H. Diaz, Gert Cauwenberghs, Tajana Rosing, Mingu Kang,"Clo-HDnn: A 4.66 TFLOPS/W and 3.78 TOPS/W Continual On-Device Learning Accelerator with Energy-Efficient Hyperdimensional Computing via Progressive Search," 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), C10-3, Kyoto, Japan, June 2025.

11. Tsung-Han Wu , Yu-Tse Shih , Hsin-Yung Fu, Chia Ling Ho, Wai-Chi Fang, Ke-Horng Chen*, Kuo-Lin Zheng, Ying-Hsi Lin , Shian-Ru Lin, Tsung-Yen Tsai, Jui Jen Wu, Meng-Fan (Marvin) Chang, "A 16.42 TOPS/mm2 Reverse Rotating Charge Sharing DRAM Compute-in-Memory Design in 28nm Process," 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, May 2025.

12. Win-San Khwa, Ping-Chun Wu, Jian-Wei Su, Chiao-Yen Cheng, Jun-Ming Hsu, Yu-Chen Chen, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Ashwin Sanjay Lele, Jui-Jen Wu, Jen-Chun Tien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*,“A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro for Edge-AI Devices,” 2025 IEEE International Solid-State Circuits Conference (ISSCC), pp. 252-253, San Francisco, CA, USA, Feb 2025.

13. De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*,“A 22nm 104.5TOPS/W μ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks,” 2025 IEEE International Solid-State Circuits Conference (ISSCC), pp. 250-251, San Francisco, CA, USA, Feb 2025.

14. Kai-Ping Lin, Tong Wu, Chang-Pao Lin, Po-Wei Chen, Zhi-Jun Zhang, Win-San Khwa, Meng-Fan Chang, Chao-Tsung Huang*,"2.9 STEP: An 8K-60fps Space-Time Resolution-Enhancement Neural-Network Processor for Next-Generation Display and Streaming," 2025 IEEE International Solid-State Circuits Conference (ISSCC), pp. 60-61, San Francisco, CA, USA, Feb 2025.

15. De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*,“A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro,” 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Jun. 2024

16. Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu. Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices,”2024 IEEE International Solid-State Circuits Conference (ISSCC) , pp. 568-570, Feb. 2024

17. Tai-Hao Wen, Hung-Hsi Hsu, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsin Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*, “A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices,”2024 IEEE International Solid-State Circuits Conference (ISSCC) , pp. 580-582, Feb. 2024

18. Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Arijit Raychowdhury Meng-Fan Chang, Arijit Raychowdhury, “A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance,”2024 IEEE International Solid-State Circuits Conference (ISSCC) , pp. 482-484, Feb. 2024

19. Ming-Yuan Song, K. L. Chen, K. M. Chen, K. T. Chang, I-Jung Wang, Yu-Cheng Hsin, Chih-Yu Lin, Elia Ambrosi, Win-San Khwa, Y. L. Lu, C. Y. Hu, Shan-Yi Yang, Shang-Han Li, Jiun-Hung Wei, Tsung-Yi Lee, Y. J. Wang, Meng-Fan Chang, C. F. Pai, Xin-Yu Bao, “High RA Dual-MTJ SOT-MRAM devices for High Speed (10ns) Compute-in-Memory Applications,”2023 International Electron Devices Meeting (IEDM), pp. 1-4, San Francisco, CA, USA, 2023

20. Tsung-En Lee, Hung-Li Chiang, Chih-Yu Chang, Yuan-Chun Su, Shu-Jui Chang, Jui-Jen Wu, Bo-Jiun Lin, Jer-Fu Wang, Shu-Chih Haw, Shang-Jui Chiu, He-Liang Ching, Yan-Gu Lin, Wei-Sheng Yun, Chen-Feng Hsu, Hengyuan Lee, Tung-Ying Lee, Matthias Passlack, Chao-Ching Cheng, Chih-Sheng Chang, H.-S. Philip Wong, Wen-Hao Chang, Meng-Fan Chang, Yu-Ming Lin, Iuliana P. Radu, “High-Endurance MoS2 FeFET with Operating Voltage Fess Than IV for eNVM in Scaled CMOS Technologies,”2023 International Electron Devices Meeting (IEDM), pp. 1-4, San Francisco, CA, USA, 2023

21. Hung-Hsi Hsu, Tai-Hao Wen, Ping-Chun Wu, Chuan-Jia Jhang, De-Qi You, Ping-Cheng Chen, Meng-Fan Chang*, “Challenges in Circuits of Nonvolatile Compute-In-Memory for Edge AI Chips,”2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 98-102, Tempe, AZ, USA, 2023

22. Luke R Upton, Akash Levy, Michael D Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina, Boris Murmann, “EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry,” 2023-IEEE 49th European Solid State Circuits Conference (ESSCIRC), pp. 469-472, Sep. 2023

23. Zexi Ji, Hanrui Wang, Miaorong Wang, Win-San Khwa, Meng-Fan Chang, Song Han, Anantha P Chandrakasan, Subhasish Mitra, Priyanka Raina, Boris Murmann, “A Fully-Integrated Energy-Scalable Transformer Accelerator Supporting Adaptive Model Configuration and Word Elimination for Language Understanding on Edge Devices,” 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 1-6, Aug. 2023

24. Samuel D Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin S Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury, “A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), C10-1, Jun. 2023

25. Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*, “A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), C10-2, Jun. 2023

26. Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Hu-Yu Chen, Chih-En Ke, Hsiu-Ming Hsiao, Shi-Hung Li, Shin-Shiang Sheu, Wei-Chung Lo, Shin-Chang Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kae-Tiong Tang, Meng-Fan Chang*, “A 22nm 832kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices,” 2023 IEEE International Solid-State Circuits Conference (ISSCC), pp. 126-128, Feb. 2023

27. Wei-Hsing Huang, Tai-Hsiang Wen, Jia-Min Hung, Win-San Khwa, Yu-Cheng Lo, Chih-Jen Jhang, Hsiang-Hsuan Hsu, Yu-Hsuan Chin, Yu-Cheng Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kae-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Chang, Meng-Fan Chang*, “A Nonvolatile AI-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W,” 2023 IEEE International Solid-State Circuits Conference (ISSCC), pp. 258-259, Feb. 2023

28. Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shoaib Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, and Arijit Raychowdhury, “A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking,” 2023 IEEE International Solid-State Circuits Conference (ISSCC), pp. 426-428, Feb. 2023

29. Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Guan-Yu Lin, Po-Jui Chen, Tsen-Hsiang Pan, De-Qing You, Fang-Yi Chen, Andrew Lee, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kae-Tiong Tang, Yu-Der Chih, Tsung-Yung Chang, Meng-Fan Chang*, “A 22nm 8Mb 46.4-160.1-TOPS/W STT-MRAM Near-Memory-Computing Macro with 8b Precision for AI-Edge Devices,” 2023 IEEE International Solid-State Circuits Conference (ISSCC), pp.496-498, Feb. 2023

30. Elia Ambrosi, Cheng-Hsien Wu, H. Y. Lee, Chen-Feng Hsu, Chien-Min Lee, Sam Vaziri, Isha M. Datye, Y. Y. Chen, D. H. Hou, Percy Chang, Dawei Heh, Pei-Jean Liao, Tung-Ying Lee, Meng-Fan Chang, Hon-Sum Philip Wong and Xin-Yu Bao, “Engineering defects in pristine amorphous chalcogenides for forming-free low voltage selectors,” IEEE International Electron Devices Meeting (IEDM), pp. 18.7.1-18.7.4, San Francisco, California, USA, Dec. 2022.

31. Matthias Passlack, Nujhat Tasneem, Zheng Wang, Khandker A. Aabrar, Jae Hur, Hang Chen, Vincent D.-H. Hou, Chih-Sheng Chang, Meng-Fan Chang, Shimeng Yu, Winston Chern, Suman Datta, Asif Khan, “Direct Quantitative Extraction of Internal Variables from Measured PUND Characteristics Providing New Key Insights into Physics and Performance of Silicon and Oxide Channel Ferroelectric FETs,” IEEE International Electron Devices Meeting (IEDM), pp. 32.4.1–32.4.4, San Francisco, California, USA, Dec. 2022.

32. Han-Wen Hu, Wei-Chen Wang, Yuan-Hao Chang, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Ming Huang, Chong-Ying Lee, Tzu-Hsiang Su, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Chung-Kuang Chen, Han-Sung Chen, Hsiang-Pang Li, Tei-Wei Kuo, Meng-Fan Chang, Keh-Chung Wang, Chun-Hsiung Hung, and Chih-Yuan Lu, “ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration,” 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 763-783, Chicago, IL, USA, Oct. 2022

33. Ming-Yuan Song, Chien-Min Lee, Shan-Yi Yang, Guan-Long Chen, Kuan-Ming Chen, I-Jung Wang, Yu-Cheng Hsin, K.-T. Chang, Chen-Feng Hsu, Shang-Han Li, Jiun-Hung Wei, Tsung-Yi Lee, Meng-Fan Chang, Xin-Yu Bao, Carlos H. Diaz, Shy-Jay Lin, “High speed (1ns) and low voltage (1.5V) demonstration of 8Kb SOT-MRAM array,” 2022 IEEE Sympos ium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 377-378, Honolulu, HI, USA, Jun. 2022

34. Hung-Li Chiang, Jer-Fu Wang, K.-H. Lin, Chih-Hung Nien, J.-J. Wu,Kuo-Yu Hsiang, Chih-Piao Chuu, Yun-Wen Chen, X.W. Zhang, Chee Wee Liu, Tahui Wang, C.-C. Wang, Min-Hung Lee, Meng-Fan Chang, Chih-Sheng Chang, Tzu-Chiang Chen, “Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array,” 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), pp. 361-362, Honolulu, HI, USA, Jun. 2022

35. Han-Wen Hu, Wei-Chen Wang, Chung-Kuang Chen, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Chao Lin, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Han-Sung Chen, Yuan-Hao Chang, Hsiang-Pang Li, Tei-Wei Kuo, Keh-Chung Wang, Meng-Fan Chang, Chun-Hsiung Hung, Chih-Yuan Lu, “A 512Gb In-Memory-Computing 3D NAND Flash Supporting Similar Vector Matching Operations on AI Edge Devices,” 2022 IEEE International Solid-State Circuits Conference (ISSCC), pp. 138-140, San Francisco, CA, USA, Feb. 2022

36. Tzu-Hsiang Hsu, Guan-Cheng Chen, Yi-Ren Chen, Chung-Chuan Lo, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh, “A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights using Mixed-mode Processing-in-Sensor Technique for Image Classification,” 2022 IEEE International Solid-State Circuits Conference (ISSCC), pp. 262-263, San Francisco, CA, USA, Feb. 2022

37. Samuel Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury, “A 40nm 64kb 26.56 TOPS/W 2.37Mb/mm2 RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and > 75% use of Sensing Dynamic Range,” 2022 IEEE International Solid-State Circuits Conference (ISSCC), pp. 268-269, San Francisco, CA, USA, Feb. 2022

38. Muya Chang, Samuel Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury, “A 40nm 60.64TOPS/W ECC Capable Compute-in-Memory/Digital 2.25MB/768KKB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems,” 2022 IEEE International Solid-State Circuits Conference (ISSCC), pp. 270-271, San Francisco, CA, USA, Feb. 2022

39. Win-San Khwa*, Yen-Cheng Chiu*, Chuan-Jia Jhang, Sheng-Po Huang, Chun-Ying Lee, Tai-Hao Wen, Fu-Chun Chang, Shao-Ming Yu, Tung-Yin Lee, Meng-Fan Chang*, “A 40nm 2M-cell 8b-Precision Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5-65.0 TOPS/W for Tiny AI Edge Devices,” 2022 IEEE International Solid-State Circuits Conference (ISSCC), pp. 180-181, San Francisco, CA, USA, Feb. 2022

40. Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*, “An 8Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4 TOPS/W - 21.6 TOPS/W for AI Edge Devices,” 2022 IEEE International Solid-State Circuits Conference (ISSCC), pp. 182-183, San Francisco, CA, USA, Feb. 2022

41. Yen-Cheng Chiu, Win-San Khwa, Chia-Sheng Yang, Shih-Hsin Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*, “A 22nm 4Mb STT-MRAM data-encrypted Near-Memory-Computation Macro with 192GB/s Read-and-Decryption Bandwidth and 25.1- 55.1 TOPS/W at 8b MAC for AI-oriented Operations,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 496-497, Feb. 2022

42. Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang*, “A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with 6.6ns Latency 1241 GOPS and 37.01 TOPS/W for 8b-MAC Operations for Edge-AI Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 190-191, Feb. 2022

43. Zhaofang Li, Syuan-Hao Sie, Jye-Luen Lee, Yi-Ren Chen, Ting-I Chou, Ping-Chun Wu, Yu-Ting Chuang, Yu-Te Lin, I-Cherng Chen, Chih-Cheng Lu, Ying-Zong Juang, Shih-Wen Chiu, Chih-Cheng Hsie, Meng-Fan Chang, Kea-Tiong Tang, “A Miniature Electronic Nose for Breath Analysis,” IEEE International Electron Devices Meeting (IEDM), pp. 35.2.1-35.2.4, Dec. 2021

44. Yu-Der Chih, Chung-Cheng Chou, Yi-Chun Shih, Chia-Fu Lee, Win-San Khwa, Chun-Yu Wu, Kuei-Hung Shen, Wen-Ting Chu, Meng-Fan Chang, Harry Chuang, Tsung-Yung Jonathan Chang, “Design Challenges and Solutions of Emerging Nonvolatile Memory for Embedded Applications,” IEEE International Electron Devices Meeting (IEDM), pp. 2.4.1-2.4.4, Dec. 2021

45. Vita Pi-Ho Hu, Chang-Ju Liu, Hung-Li Chiang, Jer-Fu Wang, Chao-Ching Cheng, Tzu-Chiang Chen, Meng-Fan Chang*, “High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing,” IEEE International Electron Devices Meeting (IEDM), pp. 8.6.1-8.6.4, Dec. 2021

46. Hung-Li Chiang, Jui-Jen Wu, Chen-Han Chou, Yen-Fu Hsiao, Yi-Chun Chen, Leo Liu, Jer-Fu Wang, Tzu-Chiang Chen, Pei-Jun Liao, Jin Cai, Xinyu Bao, Alan Cheng, Meng-Fan Chang, “Design Technology Co-Optimization for Cold CMOS Benefits in Advanced Technologies,” IEEE International Electron Devices Meeting (IEDM), pp. 13.2.1-13.2.4, Dec. 2021

47. E. Ambrosi, C. H. Wu, H. Y. Lee, P. C. Chang, C. F. Hsu, C. M. Lee, C. C. Chang, Y. Y Chen, D. W. Heh, D. H. Hou, P. J. Liao, T. Y. Lee, M. F. Chang, H.-S. P. Wong, and X. Y. Bao, “Low variability high endurance and low voltage arsenic-free selectors based on GeCTe,” IEEE International Electron Devices Meeting (IEDM), pp. 28.5.1-28.5.4, Dec. 2021

48. Xin Si, Yongliang Zhou, Jun Yang, Meng-Fan Chang*, “Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices,” 2021 IEEE 14th International Conference on ASIC (ASICON), Oct. 2021

49. Ruiqi Guo, Hao Li, Ruhui Liu, Zhixiao Zhang, Limei Tang, Hao Sun, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin, “A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation,” 2021 Symposium on VLSI Technology (VLSI Symp.), June 2021

50. Linfang Wang, Wang Ye, Jinru Lai, Jing Liu, Jianguo Yang, Xin Si, Changxing Huo, Chunmeng Dou, Xiaoxin Xu, Qi Liu, Dashan Shang, Feng Zhang, Hangbing Lv, Meng-Fan Chang, Hiroshi Iwai, “A 14nm 100Kb 2T1R Transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme,” 2021 Symposium on VLSI Technology (VLSI Symp.), June 2021

51. Ruiqi Guo, Hao Li, Ruhui Liu, Zhixiao Zhang, Limei Tang, Hao Sun, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin, “A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation,” 2021 Symposium on VLSI Circuits (VLSI Symp.), June 2021

52. W.S. Khwa, K. Akarvardar, Y. S. Chen, Y. C. Chiu, J. C. Liu, J. J. Wu, H. Y. Lee, S. M. Yu, C. H. Lee, T. C. Chen, Y. C. Lin, C. F. Hsu, T. Y. Lee, T. K. Ku, C. H. Kuo, J. Y. Wu, X. Y. Bao, C. S. Chang, Y. D. Chih, H.-S. P. Wong, Meng-Fan Chang, “MLC PCM Techniques to Improve Nerual Network Inference Retention Time by 10⁵X and Reduce Accuracy Degradation by 10.8X,” Symposium on VLSI Technology (VLSI Symp.), June 2021

53. H. L. Chiang, J.F. Wang, T. C. Chen, T. W. Chiang, C. Bair, C. Y. Tan, L. J. Huang, H. W. Yang, J. H. Chuang, H. Y. Lee, K. Chiang, K. H. Shen, Y. J. Lee, R. Wang, C. W. Liu, T. Wang, X. Bao, E. Wang, J. Cai, C. T. Lin, H. Chuang, H. S. P. Wong, Meng-Fan Chang*, “Cold MRAM as a Density Booster for Embedded NVM in Advanced Technology,” Symposium on VLSI Technology (VLSI Symp.), June 2021

54. C.H. Wu, C.M. Lee, Y. S. Chen, H. Y. Lee, E. Ambrosi, C. F. Hsu, S. Vaziri, Y. Y. Chen, C. H. Nien, R. L. Hwang, P. J. Liao, D. H. Hou, Y.-H. Lee, T. Y. Lee, T. C. Chen, Meng-Fan Chang, H.-S. P. Wong, Xinyu Bao, “Low-voltage (~1.3V), Arsenic Free Threshold Type Selector with Ultra High Endurance (> 10¹¹) for High Density 1S1R Memory Array,” Symposium on VLSI Technology (VLSI Symp.), June 2021

55. Massimo Giordano, Kartik Prabhu, …, Meng-Fan Chang, Priyanka Raina, “CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference,” Symposium on VLSI Circuits (VLSI Symp.), June 2021

56. Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury*, “A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation,” IEEE Custom Integrated Circuits Conference (CICC ), pp. 1-2, 2021

57. Yuxin Zhang, Sitao Zeng, Zhiguo Zhu, Zhaolong Qin, Chen Wang, Jingjing Li, Sanfeng Zhang, Yajuan He, Chunmeng Dou, Xin Si, Meng-Fan Chang, Qiang Li , “A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2021

58. Linfang Wang, Wang Ye, Junjie An, Chunmeng Dou, Qi Liu, Meng-Fan Chang, Ming Liu, “Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile Computing-in-Memory Based on Resistive Memory,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2021

59. Chuan-Jia Jhang, Ping-Cheng Chen, Meng-Fan Chang*, “Challenges of Computation-in-Memory Circuits for AI Edge Applications,” 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), pp. 1-2, April 2021

60. Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li, Shih-Chieh Chang , Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 28nm 384Kb 6T SRAM Computation-in-memory Macro with 8b-precision for AI Edge Chips,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 250-251, Feb. 2021

61. Cheng-Xin Xue, Je-Min Hung, Hui-Yao Kao, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Peng Chen, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*, “A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91-195.7 TOPS/W for Tiny AI Edge Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 246-247, Feb. 2021

62. Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Chang Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang, “An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications,”IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 252-253, Feb. 2021

63. Ruiqi Guo, Zhiheng Yue, Xin Si, Te Hu, Hao Li, Limei Tang, Yabing Wang, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin*, “A 5.99-to-691.1 TOPS/W Tensor-train In-Memory-Computing Processor using Bit-Level Sparsity based Optimization and Variable-Precision Quantization,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 242-243, Feb. 2021

64. Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hung, Meng-Fan Chang, Nan Sun, Xueqing Li, Huazhong Yang, Yongpan Liu*, “A 2.75-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 238-239, Feb. 2021

65. Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury*, “A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute- in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 404-405, Feb. 2021

66. Fu-Kuo Hsueh, Je-Min Hung, Sheng-Po Huang, Yen-Hsiang Huang, Cheng-Xin Xue, Chang-Hong Shen*, Jia-Min Shieh*, Wen-Cheng Chiu, Chao-Cheng Lin, Bo-Yuan Chen, Szu-Ching Liu, Shih-Wei Chen, Deng-Yan Niou, Wen-Hsien Huang, Kai-Shin Li, Kun-Kin Lin, Da-Chiang Chang, Kun-Ming Chen, Guo-Wei Huang, Ci-Ling Pan, Meng-Fan Chang*, Chenming Hu, Wen-Kuan Yeh, , “First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing Macro,” IEEE International Electron Devices Meeting (IEDM), pp.28.5.1-28.5.4, Dec. 2020

67. Akshay Krishna Ramanathan, Srivatsa Srinivasa Rangachar, Je-Min Hung, Chun-Ying Lee, Cheng-Xin Xue, ShengPo Huang, Fu-Kuo Hsueh, Chang-Hong Shen, Jia-Min Shieh, Wen-Kuan Yeh, Mon-Shu Ho, Hariram Thirucherai Govindarajan, Jack Sampson, Meng-Fan Chang* , Vijaykrishnan Narayanan, “Monolithic 3D+-IC Based Massively Parallel Compute-in-Memory Macro for Accelerating Database and Machine Learning Primitives,” IEEE International Electron Devices Meeting (IEDM), pp.40.4.1-40.4.4, Dec. 2020

68. Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Hangbing Lv, Feng Zhang, Xiaoyang Zeng, Meng-Fan Chang, Ming Liu, “A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques,” Symposium on VLSI Circuits (VLSI Symp.), June 2020

69. Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu, “A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2020

70. Cheng-Xin Xue, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Ta-Wei Liu, Shih-Ying Wei, Sheng-Po Huang, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen, Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 244-245, Feb. 2020

71. Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Zhixiao Zhang, Hongwu Jiang, Shanshi Huang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shyh-Shyuan Sheu, Sih-Han Li, Heng-Yuan Lee, Shih-Chieh Chang, Shimeng Yu, Meng-Fan Chang*, “A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 240-241, Feb. 2020

72. Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Zhixiao Zhang, Syuan-Hao Sie, Wei-Chen Wei, Yun-Chen Lo, Tai-Hsing Wen, Tzu-Hsiang Hsu, Yen-Kai Chen, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang*, “A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 246-247, Feb. 2020

73. Tung-Cheng Chang, Yen-Cheng Chiu, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Meng-Fan Chang*, “A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 224-225, Feb. 2020

74. Jinshan Yue, Zhe Yuan, Xiaoyu Feng, Yifan He, Zhixiao Zhang, Xin Si, Ruhui Liu, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu*, “A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 234-235, Feb. 2020

75. Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh*, “A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 110-111, Feb. 2020

76. Qi Liu, Bin Gao, Peng Yao, Dong Wu, Junren Chen, Yachuan Pang, Wenqiang Zhang, Yan Liao, Cheng-Xin Xue, Wei-Hao Chen, Jianshi Tang, Yu Wang, Meng-Fan Chang, He Qian, Huaqiang Wu*, “A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 500-501, Feb. 2020

77. Tzu-Hsiang Hsu, Yen-Cheng Chiu, Wei-Chen Wei, Yun-Chen Lo, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Meng-Fan Chang and Chih-Cheng Hsieh*, “AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to Device,” IEEE International Electron Devices Meeting (IEDM), pp. 530-533, Dec. 2019

78. Fu-Kuo Hsueh, Chun-Ying Lee, Cheng-Xin Xue, Chang-Hong Shen, Jia-Min Shieh, Bo-Yuan Chen, Yen-Cheng Chiu, Hsiu-Chih Chen, Ming-Hsuan Kao, Wen-Hsien Huang, Kai-Shin Li, Chien-Ting Wu, Kun-Lin Lin, Kun-Ming Chen, Guo-Wei Huang, Meng-Fan Chang Chenming Hu, and Wen-Kuan Yeh*, “Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs,” IEEE International Electron Devices Meeting (IEDM), pp.54-57, Dec. 2019

79. Zhixiao Zhang, Jia-Jing Chen, Xin Si, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Yen-Cheng Chiu, Je-Min Hong, Shyh-Shyuan Sheu, Sih-Han Li, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 217-218, Nov. 2019

80. Tzu-Hsiang Hsu, Yen-Kai Chen, Tai-Hsing Wen, Wei-Chen Wei, Yi-Ren Chen, Fu-Chun Chang, Hyunjoon Kim, Qian Chen, Bongjin Kim, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh*, “A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 33-36, Dec. 2019

81. Cheng-Xin Xue, Meng-Fan Chang*, “Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory for AI Edge Devices,” International SoC Design Conference (ISOCC), pp. 164-165, Oct. 2019

82. Xin Si, Qian He, Meng-Fan Chang, Cheng-Xin Xue, Jian-Wei Su, Zhixiao Zhang, Sih-Han Li, Shyh-Shyuan Sheu, Heng-Yuan Lee, Ping-Cheng Chen, Huaqiang Wu, “Circuit Design Challenges in Computing-in-Memory for AI Edge Devices,” IEEE 13th International Conference on ASIC (ASICON), pp. 1-4, Oct. 2019

83. Kea-Tiong Tang, Wei-Chen Wei, Zuo-Wei Yeh, Tzu-Hsiang Hsu, Yen-Cheng Chiu, Cheng-Xin Xue, Yu-Cheng Kuo, Tzu-Hao Wen, M.-S. Ho, Chih-Cheng Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Meng-Fan Chang* “Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices,” IEEE Symposium on VLSI Circuits (VLSI Symp.), C166-C167, June, 2019

84. Yen-Cheng Chiu, Han-Wen Hu, Li-Ya Lai, Tsung-Yuan Huang, Hui-Yao Kao, Kuang-Tang Chang, Mon-Shu Ho, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Chang, Meng-Fan Chang* , “A 40nm 2Mb ReRAM Macro with 85% Reduction in FORMING Time and 99% Reduction in Page-Write Time Using Auto-FORMING and Auto-Write Schemes,” IEEE Symposium on VLSI Technology (VLSI Symp.), T232-T233, June, 2019

85. Bonan Yan, Qing Yang, Wei-Hao Chen, Kung-Tang Chang, Jian-Wei Su, Chien-Hua Hsu, Sih-Han Li, Heng-Yuan Lee, Shyh-Shyuan Sheu, Mon-Shu Ho, Qihua Wu, Meng-Fan Chang, Yi Chen, Hai Li , “RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation,” IEEE Symposium on VLSI Technology (VLSI Symp.), T86-T87, June, 2019

86. Srivatsa Srinivasa, Yung-Ning Tu, Xin Si, Cheng-Xin Xue, Chun-Ying Lee, Fu-Kuo Hsueh, Chane Hone Shen, Jia-Min Shieh, Wen-Kuan Yeh, Akshay Krishna Ramanathan, Mon-Shu Ho, Jack Sampson, Meng-Fan Chang, Vijaykrishnan Narayanan , “Monolithic 3D+-IC Based Reconfigurable Compute-in-Memory SRAM Macro,” IEEE Symposium on VLSI Technology (VLSI Symp.), T32-T33, June, 2019

87. Ruiqi Guo, Yonggang Liu, Shixuan Zheng, Ssu-Yen Wu, Peng Ouyang, Win-San Khwa, Xi Chen, Jia-Jing Chen, Xiudong Li, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin, “A 5.1pJ/Neuron 127.3us/Inference RNN-Based Speech Recognition Processor Using 16 Computing-in-Memory SRAM Macros in 65nm CMOS,” Symposium on VLSI Ciruits (VLSI Symp.), pp. C120-C121, June 2019

88. Cheng-Xin Xue, Wei-Hao Chen, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Ting-Wei Chang, Tung-Cheng Chang, Tsung-Yuan Huang, Hui-Yao Kao, Shih-Ying Wei, Yen-Cheng Chiu, Chun-Ying Lee, Chung-Chuan Lo, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing time for CNN-based AI Edge Processors,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 388-390, Feb. 2019

89. Xin Si, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang*, “ATwin-8T SRAM Computation-In-Memory Macro for Multiple-bits CNN-Based Machine Learning,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 396-398, Feb. 2019

90. Jinshan Yue, Ruoyang Liu, Wenyu Sun, Zhe Yuan, Zhibo Wang, Yung-Ning Tu, Yi-Ju Chen, Ao Ren, Yanzhi Wang, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu, “A 65nm 0.39-140.3 TOPS/W 1-12bit Unified Neural Network Processor Using Block-circulant Enabled Transpose-Domain Acceleration with 8.1x Higher TOPS/mm2 and 6T HBST-TRAM Based 2D Data Reuse Architecture,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 138-140, Feb. 2019

91. Yachuan Pang, Bin Gao, Dong Wu, Shengyu Yi, Qi Liu, Wei-Hao Chen, Ting Wei Chang, Wei En Lin, Xiaoyu Sun, Shimeng Yu, He Qian, Meng-Fan Chang, Huaqiang Wu, “A Reconfigurable RRAM Physical Unclonable Function Utilizing Post-Process Randomness Source with < 6E-6 Nature Bit Error Rate,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 402-404, Feb. 2019

92. Fu-Kuo Hsueh, Wei-Hao Chen, Kai-Shin Li, Chang-Hong Shen, Jia-Min Shieh, Chun-Ying Lee, Bo-Yuan Chen, Hsiu-Chih Chen, Chih-Chao Yang, Wen-Hsien Huang, Kun-Ming Chen, Guo-Wei Huang, Peng Chen, Yung-Ning Tu, Srivatsa Srinivasa, Vijaykrishnan Narayanan, Meng-Fan Chang, Wen-Kuan Yeh, “Ultra-Low Power 3D NC-FinFET-based Monolithic 3D+-IC with Computing-in-Memory for Intelligent IoT Devices,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 15.1.1-15.1.4, Dec. 2018

93. Kai-Shin Li, Fu-Kuo Hsueh, Chang-Hong Shen, Jia-Min Shieh, Hsiu-Chih Chen, Wen-Hsien Huang, Hsiao-Yun Chiu, Chih-Chao Yang, Tung-Ying Hsieh, Bo-Yuan Chen, Wei-Hao Chen, Kuo-Hsiang Hsu, Meng-Fan Chang, Wen-Kuan Yeh, “FinFET-based Monolithic 3D+ with RRAM Array and Computing in Memory SRAM for Intelligent IoT Chip Application,” 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-3, 2018

94. Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, “DL-RSIM: A Simulation Framework to Enable Reliable ReRAM-based Accelerators for Deep Learning ,” (ICCAD), pp. 1-8, 2018

95. Pin-Yi Li, Cheng-Han Yang, Wei-Hao Chen, Jian-Hao Huang, Wei-Chen Wei, Je-Syu Liu, Wei-Yu Lin, Zu- Hsiang Hs, Chih-Cheng Hsieh, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang*, “A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array,” IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 1-4, 2018

96. Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi and Meng-Fan Chang, “A 28nm 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell,” IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 127-128, Nov. 2018

97. Chun-Meng Dou, Wei-Hao Chen, Cheng-Xin Xue, Wei-Yu Lin, Wei-En Lin, Jun-Yi Li, Huan-Ting Lin, Meng-Fan Chang*, “Nonvolatile Circuits-Devices Interaction for Memory, Logic and Artificial Intelligence,” Symposium on VLSI Technology (VLSI Symp.), pp. 171-172, June 2018 (invited)

98. Zhe Yuan, Jinshan Yue, Huarui Yang, Zhibo Wang, Jinyang Li, Yixiong Yang, Qinwei Guo, Xueqing Li, Meng-Fan Chang, Huazhong Yang, Yongpan Liu, “Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers,” Symposium on VLSI Circuits (VLSI Symp.), pp. 33-34, June 2018

99. Rui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu, “Parallelizing SRAM Arrays with Customized Bit-Cell for Binary Neural Networks,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2018

100. Yixiong Yang, Zhibo Wang, Pei Yang, Meng-Fan Chang, Mon-Shu Ho, Huazhong Yang, Yongpan Liu, “A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2018

101. Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with sub-16ns Multiply-and-Accumulate for Binary DNN AI Edge Processors,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 494-495, Feb. 2018

102. Win-San Khwa, Jia-Jing Chen, Jia-Fang Li, Xin Si, En-Yu Yang, Xiaoyu Sun, Rui Liu, Pai-Yu Chen, Qiang Li, Shimeng Yu, Meng-Fan Chang*, “A 65nm 4Kb Algorithm-Dependent Computing-in-Memory SRAM Unit-Macro with 2.3ns and 55.8 TOPS/W Fully Parallel Product-Sum Operation for Binary DNN Edge Processors,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 496-497, Feb. 2018

103. Tzu-Hsien Yang, Kai-Xiang Li, Yen-Ning Chiang, Wei-Yu Lin, Huan-Ting Lin, Meng-Fan Chang*, “A 28nm 32Kb Embedded 2T2MTJ STT-MRAM Macro with 1.3ns Read-Access-Time for Fast and Reliable Read Applications,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 480-481, Feb. 2018

104. Wei-Hao Chen, Wen-Jang Lin, Li-Ya Lai, Shuangchen Li, Chien-Hua Hsu, Huan-Ting Lin, Heng-Yuan Lee, Jian-Wei Su, Yuan Xie, Shyh-Shyuan Sheu, Meng-Fan Chang*, “A 16Mb Dual-Mode ReRAM Macro with Sub-14ns Computing-In-Memory and Memory Functions Enabled by Self-Write Termination Scheme,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 28.2.1-28.2.4, Dec. 2017

105. Fu-Kuo Hsueh, Hsiao Yun Chiu, Chang Hong Shen, Jia Min Shieh, Ying Tsan Tang, Chih Chao Yang, Hsiu Chih Chen, Wen Hsien Huang, Bo-Yuan Chen, Kun-Ming Chen, Guo-Wei Huang, Wei-Hao Chen, Kuo Hsiang Hsu, Srivatsa Rangachar Srinivasa, Nicholas Jao, Albert Lee, Hochul Lee, Vijaykrishnan Narayanan, Kang Lung Wang, Meng-Fan Chang, Wen-Kuan Yeh, “TSV-free FinFET-based Monolithic 3D+-IC with Computing-in-Memory SRAM Cell for Intelligent IoT Devices,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 12.6.1-12.6.4, Dec. 2017

106. Feng Zhang, Dongyu Fan, Yuan Duan, Jin Li, Cong Fang, Yun Li, Xiaowei Han, Lan Dai, Chengying Chen, Jinshun Bi, Ming Liu, Meng-Fan Chang*, “A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range ,” 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 173-176, Nov. 2017

107. Chunmeng Dou, Wei-Hao Chen, Yi-Ju Chen, Huan-Ting Lin, Wei-Yu Lin, Mon-Shu Ho, Meng-Fan Chang*, “Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing,” IEEE 12th International Conference on ASIC (ASICON), pp. 140-143, Oct. 2017 (Invited Talk/Paper)

108. Srivatsa Rangachar Srinivasa, Karthik Mohan, Wei-Hao Chen, Kuo-Hsinag Hsu, Xueqing Li, Meng-Fan Chang, Sumeet Kumar Gupta, John Sampson, Vijaykrishnan Narayanan, “Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via,” 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp128-133, 2017

109. Chieh-Pu Lo, Wen-Zhang Lin, Wei-Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya-Chin King, Chrong-Jung Lin, Yu-Der Chih, Tsung-Yung Jonathon Chang, Mon-Shu Ho, Meng-Fan Chang*, “Embedded 2Mb ReRAM Macro with 2.6ns Read Access Time Using Dynamic- Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier for IoE Applications,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. C164-C165, June 2017

110. Fang Su, Wei-Hao Chen, Lixue Xia, Chieh-Pu Lo, Tianqi Tang, Zhibo Wang, Kuo-Hsiang Hsu, Ming Cheng, Jun-Yi Li, Yuan Xie, Yu Wang, Meng-Fan Chang, Huazhong Yang, Yongpan Liu, “A 462GOPs/J RRAM-Based Nonvolatile Intelligent Processor for Energy Harvesting IoE System Featuring Nonvolatile Logics and Processing-In-Memory,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. T260-T261, June 2017

111. Fang Su, Meng-Fan Chang, Huazhong Yang, Yongpan Liu, “A 130nm FeRAM-Based Energy Harvesting Nonvolatile System-On-Chip with 5.2x Higher Performance & 26.9x Faster System Wakeup Using Adaptive Load Balance and Fast Peripheral Startup Schemes,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. C260-C261, June 2017

112. Wei-Hao Chen, Win-San Khwa, Jun-Yi Li, Wei-Yu Lin, Huan-Ting Lin, Yongpan Liu, Yu Wang, Huaqiang Wu, Huazhong Yang, Meng-Fan Chang*, “Circuit Design for Beyond Von Neumann Applications Using Emerging Memory: From Nonvolatile Logics to Neuromorphic Computing,” in Proc. International Symposium on Quality Electronic Design (ISQED), pp. 23-28 March 2017 (Invited Paper/special session)

113. Chieh-Pu Lo, Wei-Hao Chen, Zhibo Wang, Albert Lee, Kuo-Hsiang Hsu, Fang Su, Ya-Chin King, Chrong Jung Lin, Yongpan Liu, Huazhong Yang, Pedram Khalili, Kang-Lung Wang, Meng-Fan Chang*, “A ReRAM-based Single-NVM Nonvolatile Flip-Flop with Reduced Stress-Time and Write-Power against Wide Distribution in Write-Time by Using Self-Write-Termination Scheme for Nonvolatile Processors in IoT Era,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 16.3.1-16.3.4, Dec. 2016

114. Ra-Min Tain, Dyi-Chung Hu, Kai-Ming Yang, Yu-Hua Chen, Chih-Lun Wang, Cheng-Hsiung Wang, Ching Chang, Yan-bin Chang, Zih-Yu Ciou, Han-Wen Hu, Meng-Fan Chang*, “SiP assembly and application using glass substrate with through vias,” 2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), pp. 281-284, 2016

115. Fang Su, Zhibo Wang, Jinyang Li, Meng-Fan Chang, Yongpan Liu, “Design of nonvolatile processors and applications,” 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1-6, 2016

116. Meng-Fan Chang*, Shin-Jang Shen, Yi-Lun Lu, Yih-Shan Yang, Jui-Yu Hung, Che-Wei Wu, Yan-Bing Zhang, Wei-How Chen, Han-Wen Hu, “A sub-0.5V charge pump circuit for resistive RAM (ReRAM) enabled low supply voltage nonvolatile logics and nonvoaltile processors,” in Proc. IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 342-345, Aug. 2016 (invited)

117. Sumitha George, Kaisheng Ma, Ahmedullah Aziz, Xueqing Li, Asif Islam Khan, Sayeef S. Salahuddin, Meng-Fan Chang, Suman Datta, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan, “Nonvolatile Memory Design Based on Ferroelectric FETs,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2016

118. Meng-Fan Chang*, Ching-Hao Chuang, Yen-Ning Chiang, Shyh-Shyuan Sheu, Chia-Chen Kuo, Hsiang-Yun Cheng, John Sampson, Mary Jane Irwin, “Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1142-1145, May 2016. (invited)

119. Ming-Hsuan Kao, Chih-Chao Yang, Tsung-Ta Wu, Tung-Ying Hsieh, Wen-Hsien Huang, Hsing-Hsiang Wang, Chang-Hong Shen, Wen-Kuan Yeh, Meng-Fan Chang, Jia-Min Shieh, “A-SiGeC thin film photovoltaic enabled self-power monolithic 3D IC under indoor illumination,” in Proc. IEEE International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), pp. 1-2, April 2016

120. Chien-Chen Lin, Jui-Yu Hung, Wen-Zhang Lin, Chieh-Pu Lo, Yen-Ning Chiang, Hsiang-Jen Tsai, Geng-Hau Yang, Ya-Chin King, Chrong Jung Lin, Tien-Fu Chen, Meng-Fan Chang*, “A 256b-Wordlength ReRAM-based TCAM with 1ns Search-Time and 14x Improvement in WordLength-EnergyEfficiency-Density Product using 2.5T1R cell,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 136-137, Feb. 2016

121. Win-San Khwa, Meng-Fan Chang, Jau-Yi Wu, Ming-Hsiu Lee, Tzu-Hsiang Su, Keng-Hao Yang, Tien-Fu Chen, Tien-Yen Wang, Hsiang-Pang Li, Matthew Brightsky, Sangbum Kim, Hsiang-Lam Lung, Chung Lam, “A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100X for Storage Class Memory Applications,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 134-135, Feb. 2016

122. Yongpan Liu, Zhibo Wang, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Chien-Chen Lin, Qi Wei, Yu Wang, Ya-Chin King, Chrong-Jung Lin, Pedram Khalili Amiri, Kang-Lung Wang, Meng-Fan Chang, Huazhong Yang, “A 65nm ReRAM-Enabled Nonvolatile Processor with 6X Reduction in Restore Time and 4X Higher Clock Frequency Using Adaptive Data Retention and Self-Write-Termination Nonvolatile Logic,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 84-85, Feb. 2016

123. Tsung Ta Wu, Chang Hong Shen, Jia Min Shieh, Wen Hsien Huang, Hsing Hsiang Wang, Fu Kuo Hsueh, Hisu Chih Chen, Chih Chao Yang, Tung Ying Hsieh, Bo Yuan Chen, Yu Shao Shiao, Chao Shun Yang, Guo Wei Huang, Kai Shin Li, Ting Jen Hsueh, Chien Fu Chen, Wei Hao Chen, Fu Liang Yang, Meng-Fan Chang, Wen Kuan Yeh, “Low-Cost and TSV-free Monolithic 3D-IC with Heterogeneous Integration of Logic, Memory and Sensor Analogy Circuitry for Internet of Things,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 25.4.1-25.4.4, Dec. 2015

124. Albert Lee, Meng-Fan Chang*, Chien-Chen Lin, Chien-Fu Chen, Mon-Shu Ho, Chia-Chen Kuo, Pei-Ling Tseng, Shyh-Shyuan Sheu, Tzu-Kun Ku, “ReRAM-based 7T1R Nonvolatile SRAM with 2x Reduction in Store Energy and 94x Reduction in Restore Energy for Frequent-Off Instant-On Applications,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. C76-C77, June 2015

125. Meng-Fan Chang*, Wang-Ying Lu, Shin-Jang Shen, Ming-Pin Chen, Chih-Sheng Lin, S.-S. Sheu, C.-H. Hung, Y.-S. Yang, Y.-J. Kuo, S.-N. Hung, H.-T. Lue, Chang-Hong Shen, Jia-Min Shieh, “Supply-Variation-Resilient Nonvolatile 3D IC and 3D Memory Using Low Peak-Current On-Chip Charge-Pump Circuits,” in Proc. IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 118-121, June 2015

126. Hsiang-Jen Tsai, Keng-Hao Yang, Yin-Chi Peng, Chien-Chen Lin, Ya-Han Tsao, Meng-Fan Chang, Tien-Fu Chen, “Energy-Efficient Non-Volatile TCAM Search Engine Design Using Priority-Decision in Memory Technology for DPI,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2015

127. Yongpan Liu, Zewei Li, Hehe Li, Yiqun Wang, Xueqing Li, Kaisheng Ma, Shuangchen Li, Meng-Fan Chang, Sampson John, Yuan Xie, Jiwu Shu, Huazhong Yang, “Ambient Energy Harvesting Nonvolatile Processors: From Circuit to System,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2015

128. Albert Lee, Chien-Chen Lin, Ting-Chin Yang, Meng-Fan Chang, “An embedded ReRAM Using a Small-offset Sense Amplifier for Low-Voltage Operations,” in Proc. IEEE International Symposium on VLSI Design, Automation and Testing (VLSI-DAT), pp. 1-4, Apr. 2015

129. Hehe Li, Yongpan Liu, Qinghang Zhao, Yizi Gu, Xiao Sheng, Guangyu Sun, Chao Zhang, Meng-Fan Chang, Rong Luo, Huazhong Yang, “An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes,” in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 7-12, Mar. 2015

130. Meng-Fan Chang*, Chien-Fu Chen, Ting-Hao Chang, Chi-Chang Shuai, Yen-Yao Wang, Hiroyuki Yamauchi, “A 28nm 256Kb 6T-SRAM with 280mV Improvement in VMIN Using a Dual-Split-Control Assist Scheme,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 314-315, Feb. 2015

131. Meng-Fan Chang*, Chien-Chen Lin, Albert Lee, Chia-Chen Kuo, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Pei-Ling Tseng, Heng-Yuan Lee, Tzu-Kun Ku, “A 3T1R Nonvolatile TCAM Using MLC ReRAM with Sub-1ns Search Time,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 318-319, Feb. 2015

132. Meng-Fan Chang*, Chien-Chen Lin, Chien-Fu Chen, Pei-Ling Tseng, Shyh-Shyuan Sheu, Tzu-Kun Ku, Mon-Shu Ho, “Challenges at Sensing Circuits for Resistive Memory and Memristor-based Nonvolatile Logics,” in Proc. 2014 IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp. 569–574, Jan. 2015 (Invited Talk/Paper) (Tokyo, Japan)

133. Chang-Hong Shen, Jia-Min Shieh, Wen-Hsien Huang, Tsung-Ta Wu, Chien-Fu Chen, Ming-Hsuan Kao, Chih-Chao Yang, Chein-Din Lin, Hsing-Hsiang Wang, Tung-Yang Hsieh, Bo-Yuan Chen, Guo-Wei Huang, Meng-Fan Chang, Fu-Liang Yang, “Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 3.6.1-3.6.4, Dec. 2014

134. Win-San Khwa, Jau-Yi Wu, Tzu-Hsiang Su, Hsiang-Pang Li, Matthew BrightSky, Tien-Yen Wang, T. H. Hsu, Pei-Ying Du, Sangbum Kim, W. Chien, Huai-Yu Cheng, R. Cheek, E. Lai, Yu Zhu, M. H. Lee, Meng-Fan Chang, H. Lung, Chung Lam, “Novel Inspection and Annealing Procedure to Rejuvenate Phase Change Memory from Cycling-Induced Degradations for Storage Class Memory Applications,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 29.8.1-29.8.4, Dec. 2014

135. Meng-Fan Chang*, Che-Wei Wu, Jui-Yu Hung, Ya-Chin King, Chorng-Jung Lin, Mon-Shu Ho, Chia-Chen Kuo, Shyh-Shyuan Sheu, “A Low-Power Subthreshold-to-Superthreshold Level-Shifter for Sub-0.5V Embedded Resistive RAM (ReRAM) Macro in Ultra Low-Voltage Chips,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 695-698, Oct. 2014 (Best Paper Award)

136. Wen-Pin Lin, Shyh-Shyuan Sheu, Chia-Chen Kuo, Pei-Ling Tseng, Meng-Fan Chang, Keng-Li Su, Chih-Sheng Lin, Kan-Hsueh Tsai, Sih-Han Lee, Szu-Chieh Liu, Yu-Sheng Chen, Heng-Yuan Lee, Ching-Chih Hsu, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao, “A nonvolatile look-up table using ReRAM for reconfigurable logic,” in Proc. IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 133-136, Nov. 2014

137. Meng-Fan Chang*, Albert Lee, Chia-Chen Kuo, Shyh-Shyuan Sheu, Frederick T. Chen, Tzu-Kun Ku, Yong-Pan Liu, Hua-Zhong Yang, Ping-Cheng Chen, “Challenges at Circuit Designs for Resistive-Type Nonvolatile Memory and Nonvolatile Logics in Mobile and Cloud Applications,” in Proc. IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1-4, Oct. 2014 (Invited Talk/Paper)

138. Li-Yue Huang, Meng-Fan Chang*, Ching-Hao Chuang, Chia-Chen Kuo, Chien-Fu Chen, Gwo-Huang Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Keng-Li Su, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao, “ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 122-123, June 2014 (Hawaii, US)

139. Hsiang-Jen Tsai, Chien-Chih Chen, Keng-Hao Yang, Ting-Chin Yang, Li-Yue Huang, Ching-Hao Chung, Meng-Fan Chang, Tien-Fu Chen, “Leveraging Data Lifetime for Energy-aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination,” in Proc. IEEE Design Automation Conference (DAC), pp. 1-6, June 2014

140. Meng-Fan Chang*, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chorng-Jung Lin, Ku-Feng Lin, Yu-Der Chih, Sreedhar Natarajan, Tsung-Yung Jonathan Chang, “Embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V Read Using Swing-Sample-and-Couple Sense Amplifier and Self-Boost-Write-Termination Scheme,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 332-333, Feb. 2014

141. Kea-Tiong Tang, Shih-Wen Chiu, Chung-Hung Shih, Chia-Ling Chang, Chia-Min Yang, Da-Jeng Yao, Jen-Huo Wang, Chien-Ming Huang, Hsin Chen, Kwuang-Han Chang, Chih-Cheng Hsieh, Ting-Hau Chang, Meng-Fan Chang, Chia-Min Wang, Yi-Wen Liu, Tsan-Jieh Chen, Chia-Hsiang Yang, Herming Chiueh, Jyuo-Min Shyu, “A 0.5V 1.27mW Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 420-421, Feb. 2014

142. Chang-Hong Shen, Jia-Min Shieh, Wen-Hsien Huang, Tsung-Ta Wu, Bo-Yuan Chen, Guo-Wei Huang, Yu-Chuan Lien, Chien-Fu Chen, Meng-Fan Chang, Chen Hu, Fu-Liang Yang, “Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 232 – 235, Dec. 2013

143. Yen-Cheng Liu, Meng-Fan Chang*, Yu-Fan Lin, Jui-Jen Wu, Che-Ju Yeh, Shin-Jang Shen, Ping-Cheng Chen, Wu-Chin Tsai, Yu-Der Chih, Sreedhar Natarajan, “An Embedded Flash Macro with Sub-4ns Random-Read-Access Using Asymmetric-Voltage- Biased Current-Mode Sensing Scheme,” in Proc. IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 241-244, Nov. 2013 (Singapore)

144. Shyh-Shyuan Sheu, Chia-Chen Kuo, Meng-Fan Chang, Pei-Ling Tseng, Chih-Sheng Lin, Min-Chuan Wang, Chih-He Lin, Wen-Pin Lin, Tsai-Kan Chien, Sih-Han Lee, Szu-Chieh Liu, Heng-Yuan Lee, Pang-Shiu Chen, Yu-Sheng Chen, Ching-Chih Hsu, Frederick T. Chen, Keng-Li Su, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao, “A ReRAM Integrated 7T2R Non-volatile SRAM for Normally-off Computing Application,” in Proc. IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 245-248, Nov. 2013 (Singapore)

145. Meng-Fan Chang*, Chia-Cheng Kuo, Shyh-Shyuan Sheu, Chorng-Jung Lin, Ya-Chin King, Zhe-Hui Lin, Keng-Li Su, Yu-Sheng Chen, Wen-Pin Lin, Heng-Yuan Lee, Chen-Han Tsai, Wei-Su Chen, Frederick T. Chen, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai, Jui-Jen Wu, Yu-Der Chih, Sreedhar Natarajan, “Area-Efficient Embedded RRAM Macros with Sub-5ns Random-Read-Access-Time Using Logic-Process Parasitic-BJT-Switch (0T1R) Cell and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 112-113, June 2013 (Kyoto, Japan)

146. Chun-Hsiung Hung, Yih-Shan Yang, Yao-Jen Kuo, Tzu-Neng Lai, Shin-Jang Shen, Jo-Yu Hsu, Shuo-Nan Hung, Hang-Ting Lue, Meng-Fan Chang*, Yen-Hao Shih, Shih-Lin Huang, Ti-Wen Chen, Tzung-Shen Chen, Chung-Kuang Chen, Chi-Yu Hung, Chih-Yuan Lu, “3D Stackable Vertical-Gate BE-SONOS NAND Flash with Layer-Aware Program-and-Read Schemes and Wave-Propagation Fail-Bit-Detection against Cross-Layer Process Variations,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 20-21, June 2013 (Kyoto, Japan)

147. Chien-Fu Chen, Ting-Hao Chang, Lai-Fu Chen, Meng-Fan Chang*, Hiroyuki Yamauchi, “A 210mV 7.3MHz 8T SRAM with Dual Data-Aware Write-Assists and Negative Read Wordline for High Cell-Stability, Speed and Area-Efficiency,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 130-131, June 2013 (Kyoto, Japan)

148. Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang*, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Mon-Shu Ho, Heng-Yuan Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi, “A 260mV L-shaped 7T SRAM with Bit-Line (BL) Swing Expansion Schemes Based on Boosted BL, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 112-113, June 2012 (Hawaii, US)

149. Meng-Fan Chang*, Che-Wei Wu, Chia-Cheng Kuo, Shin-Jang Shen, Ku-Feng Lin, Shu-Meng Yang, Ya-Chin King, Chorng-Jung Lin, Yu-Der Chih, “A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low Voltage Current-Mode Sensing Scheme with 45ns Random Read Time,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 434-435, Feb. 2012

150. Kea-Tiong Tang, Shih-Wen Chiu, Meng-Fan Chang, Chih-Cheng Hsieh, Jyuo-Min Shyu, “A wearable Electronic Nose SoC for healthier living,” 2011 IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 293-296, Nov. 2011

151. Meng-Fan Chang*, Pi-Feng Chiu, Wei-Cheng Wu, Ching-Hao Chuang, Shyh-Shyuan Sheu, “Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM),” in Proc. IEEE International Conference on ASIC (ASICON), pp. 299-302, Oct. 2011

152. Meng-Fan Chang*, Wei-Cheng Wu, Chih-Sheng Lin, Pi-Feng Chiu, Ming-Bin Chen, Yen-Huei Chen, Hsin-Chi Lai, Zhe-Hui Lin, Shyh-Shyuan Sheu, Tzu-Kun Ku, Hiroyuki Yamauchi, “A Larger Stacked Layer Number Scalable TSV-based 3D-SRAM for High-Performance Universal-Memory-Capacity 3D-IC Platforms,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 74-75, June 2011 (Kyoto, Japan)

153. Yu-Hsin Chen, Shu-Yu Chou, Qiang Lee, Wei-Ming Chan, Dan Sun, Hsin-Ju Liao, Pei-Hua Wang, Meng-Fan Chang, Hiroyuki Yamauchi, “A 40nm Fully Functional SRAM with BL Swing and WL Pulse Measurement Scheme for Eliminating a Need for Additional Sensing Tolerance Margins,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 70-71, June 2011 (Kyoto, Japan)

154. Meng-Fan Chang*, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Shang-Chi Wu, Chia-En Huang, Han-Chao Lai, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi, “An offset tolerant current-sampling-based sense amplifier for sub-100nA-cell-current nonvolatile memory,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 206-207, Feb 2011

155. Shyh-Shyuan Sheu, Meng-Fan Chang*, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai, “A 4Mb embedded SLC Resistive-RAM macro with 7.2ns read-write random access time and 160ns MLC-access capability,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 200-201, Feb 2011

156. Ching-Hua Wang, Yi-Hung Tsai, Kai-Chun Lin, Meng-Fan Chang, Ya-Chin King, Chorng-Jung Lin, Shyh-Shyuan Sheu, Yu-Sheng Chen, Heng-Yuan Lee, Frederick T. Chen, Ming-Jinn Tsai, “3-Dimensional 4F2 ReRAM Cell with CMOS Logic Compatible Process,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 29.6.1-29.6.4, Dec. 2010

157. Pi-Feng Chiu, Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Pei-Chia Chiang, Che-Wei Wu, Wen-Pin Lin, Che-He Lin, Ching-Chih Hsu, Frederick T. Chen, Keng-Li Su, Ming-Jer Kao, Ming-Jinn Tsai, “A Low Store Energy, Low VDDmin, Nonvolatile 8T2R SRAM with 3D Stacked RRAM Devices for Low Power Mobile Applications,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 229-230, June 2010 (Hawaii, US)

158. Jui-Jen Wu, Yen-Hui Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi, “A Large ̓VTH/VDD Tolerant Zigzag 8T SRAM with Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 103-104, June 2010 (Hawaii, US)

159. Meng-Fan Chang*, Shu-Meng Yang, Chih-Wei Liang, Chi-Chyuang Chiang, Pi-Feng Chiu, Ku-Feng Lin, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi, “A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 266-267, Feb 2010 (San Francisco, US)

160. Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Hiroyuki Yamauchi, “A differential data aware power-supplied (D2AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 156-157, June 2009 (Kyoto, Japan)

161. Meng-Fan Chang*, Shu-Meng Yang, Kuang-Ting Chen, Hung-Jen Liao, Robin Lee, “Improving the speed and power of compilable SRAM using dual-mode self-timed technique,” in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), pp. 57-60, Dec. 2007

162. Meng-Fan Chang*, Ding-Ming Kwai, Sue-Meng Yang, Yung-Fa Chou, Ping-Cheng Chen, “Experiments on reducing standby current for compilable SRAM using hidden clustered source line control,” in Proc. IEEE International Conference on ASIC (ASICON), pp. 1038-1041, Oct. 2007

163. Ding-Ming Kwai, Yung-Fa Chou, Meng-Fan Chang, Su-Meng Yang, Ding-Sheng Chen, Min-Chung Hsu, Yu-Zhen Liao, Shiao-Yi Lin, Yu-Ling Sung, Chia-Hsin Lee, Hsin-Kun Hsu, “FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment,” in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), pp. 28-33, Aug. 2006

164. Meng-Fan Chang*, Ding-Ming Kwai, Kuei-Ann Wen, “Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique,” in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), pp. 16-21, Aug. 2005

165. Meng-Fan Chang*, Lih-Yih Chiou, Kuei-Ann Wen, “A low supply noise content sensitive ROM architecture for SoC,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 1021-1024, Dec. 2004

166. Meng-Fan Chang*, Kuei-Ann Wen, Ding-Ming Kwai, “Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs,” in Proc. IEEE Int’l Symp. Quality Electronic Design (ISQED), pp. 297-302, Mar. 2004 (Oral)