Publications

Journal Papers

Conference Papers

Patents

Book Chapters and others

 

Highlights (updated on April 2024)

l   100+ top conference papers: ISSCC (48), VLSI Symp. (34), IEDM (22), DAC (7)

Conference Papers (研討會論文)

  1. W-S. Khwa, P-C. Wu, J-W. Su, C-Y. Cheng, J-M. Hsu, Y-C. Chen, L-J. Hsieh, J-C. Bai, Y-S. Kao, T-H. Lou, A. S. Lele, J-J. Wu, J-C. Tien, C-C. Lo, R-S. Liu, C-C. Hsieh, K-T. Tang, Meng-Fan Chang,“A 16nm 216kb, 188.4TOPS/W and 133.5TFLOPS/W Microscaling Multi-Mode Gain-Cell CIM Macro for Edge-AI Devices,” 2025 IEEE International Solid-State Circuits Conference (ISSCC), Accepted

  2. De-Qi You, Win-San Khwa, Bo Zhang, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Yi-Ming Li, Yu-Hui Wang, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang,“A 22nm 104.5TOPS/W μ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks,” 2025 IEEE International Solid-State Circuits Conference (ISSCC), Accepted

  3. De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang,“A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro,” 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Symp.), pp. 1-2, Jun. 2024

  4. Win-San Khwa, Ping-Chun Wu, Jui-Jen Wu, Jian-Wei Su, Ho-Yu Chen, Zhao-En Ke, Ting-Chien Chiu, Jun-Ming Hsu. Chiao-Yen Cheng, Yu-Chen Chen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang, “A 16nm 96Kb Integer/Floating-Point Dual-Mode-Gain-Cell-Computing-in-Memory Macro Achieving 73.3-163.3TOPS/W and 33.2-91.2TFLOPS/W for AI-Edge Devices,”2024 IEEE International Solid-State Circuits Conference (ISSCC) , pp. 568-570, Feb. 2024

  5. Tai-Hao Wen, Hung-Hsi Hsu, Win-San Khwa, Wei-Hsing Huang, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Yu-Chen Chang, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shih-Hsin Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang, “A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices,”2024 IEEE International Solid-State Circuits Conference (ISSCC) , pp. 580-582, Feb. 2024

  6. Samuel D. Spetalnick, Ashwin Sanjay Lele, Brian Crafton, Muya Chang, Sigang Ryu, Jong-Hyeok Yoon, Zhijian Hao, Azadeh Ansari, Win-San Khwa, Yu-Der Chih, Arijit Raychowdhury Meng-Fan Chang, Arijit Raychowdhury, “A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance,”2024 IEEE International Solid-State Circuits Conference (ISSCC) , pp. 482-484, Feb. 2024

  7. M. Y. Song, K. L. Chen, K. M. Chen, K. T. Chang, I. J. Wang, Y. C. Hsin, C. Y. Lin, E. Ambrosi, Win-San Khwa, Y. L. Lu, C. Y. Hu, S. Y. Yang, S. H. Li, J. H. Wei, T. Y. Lee, Y. J. Wang, M. F. Chang, C. F. Pai, X. Y. Bao, “High RA Dual-MTJ SOT-MRAM devices for High Speed (10ns) Compute-in-Memory Applications,”2023 International Electron Devices Meeting (IEDM)

  8. Tsung-En Lee, Hung-Li Chiang, Chih-Yu Chang, Yuan-Chun Su, Shu-Jui Chang, Jui-Jen Wu, Bo-Jiun Lin, Jer-Fu Wang, Shu-Chih Haw, Shang-Jui Chiu, He-Liang Ching, Yan-Gu Lin, Wei-Sheng Yun, Chen-Feng Hsu, Hengyuan Lee, Tung-Ying Lee, Matthias Passlack, Chao-Ching Cheng, Chih-Sheng Chang, H.-S. Philip Wong, Wen-Hao Chang, Meng-Fan Chang, Yu-Ming Lin, Iuliana P. Radu, “High-Endurance MoS2 FeFET with Operating Voltage Fess Than IV for eNVM in Scaled CMOS Technologies,”2023 International Electron Devices Meeting (IEDM)

  9. Hung-Hsi Hsu, Tai-Hao Wen, Ping-Chun Wu, Chuan-Jia Jhang, De-Qi You, Ping-Cheng Chen, Meng-Fan Chang, “Challenges in Circuits of Nonvolatile Compute-In-Memory for Edge AI Chips,”2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS)

  10. Luke R Upton, Akash Levy, Michael D Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina, Boris Murmann, “EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry,” 2023-IEEE 49th European Solid State Circuits Conference (ESSCIRC), pp. 469-472, Sep. 2023

  11. Zexi Ji, Hanrui Wang, Miaorong Wang, Win-San Khwa, Meng-Fan Chang, Song Han, Anantha P Chandrakasan, Subhasish Mitra, Priyanka Raina, Boris Murmann, “A Fully-Integrated Energy-Scalable Transformer Accelerator Supporting Adaptive Model Configuration and Word Elimination for Language Understanding on Edge Devices,” 2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 1-6, Aug. 2023

  12. Samuel D Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin S Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury, “A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Symp.), pp. 1-2, June 2023

  13. Tai-Hao Wen, Je-Min Hung, Hung-Hsi Hsu, Yuan Wu, Fu-Chun Chang, Chung-Yuan Li, Chih-Han Chien, Chin-I Su, Win-San Khwa, Jui-Jen Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang, “A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Symp.), pp. 1-2, June 2023

  14. P-C. Wu, J-W. Su, L-Y. Hong, J-S. Ren, C-H. Chien, H-Y. Chen, C-E. Ke, H-M. Hsiao, S-H. Li, S-S. Sheu, W-C. Lo, S-C. Chang, C-C. Lo, R-S. Liu, C-C. Hsieh, K-T. Tang, M-F. Chang, “A 22nm 832kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 126-128, Feb. 2023

  15. W-H. Huang, T-H. Wen, J-M. Hung, W-S. Khwa, Y-C. Lo, C-J. Jhang, H-H. Hsu, Y-H. Chin, Y-C. Chen, C-C. Lo, R-S. Liu, K-T. Tang, C-C. Hsieh, Y-D. Chih, T-Y. Chang, M-F. Chang, “A Nonvolatile AI-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 15-17, Feb. 2023

  16. M. Chang, A. S. Lele, S. D. Spetalnick, B. Crafton, S. Konno, Z. Wan, A. Bhat, W-S. Khwa, Y-D. Chih, M-F. Chang, A. Raychowdhury, “A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 426-428, Feb. 2023

  17. Y-C. Chiu, W-S. Khwa, C-Y. Li, F-L. Hsieh, Y-A. Chien, G-Y. Lin, P-J. Chen, T-H. Pan, D-Q. You, F-Y. Chen, A. Lee, C-C. Lo, R-S. Liu, C-C. Hsieh, K-T. Tang, Y-D. Chih, T-Y. Chang, M-F. Chang, “A 22nm 8Mb 46.4-160.1-TOPS/W STT-MRAM Near-Memory-Computing Macro with 8b Precision for AI-Edge Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp.496-498, Feb. 2023

  18. E. Ambrosi, C. H. Wu, H. Y. Lee, C. F. Hsu, C. M. Lee, S. Vaziri, I. M. Datye, Y. Y. Chen, D. H. Hou, P. C. Chang, D. W. Heh, P. J. Liao, T. Y. Lee, M. F. Chang, H.-S. P. Wong and X. Y. Bao, “Engineering defects in pristine amorphous chalcogenides for forming-free low voltage selectors,” IEEE International Electron Devices Meeting (IEDM), pp. 18.7.1-18.7.4, Dec. 2022

  19. Matthias Passlack, Nujhat Tasneem, Zheng Wang, Khandker A. Aabrar, Jae Hur, Hang Chen, Vincent D.-H. Hou, Chih-Sheng Chang, Meng-Fan Chang, Shimeng Yu, Winston Chern, Suman Datta, Asif Khan, “Direct Quantitative Extraction of Internal Variables from Measured PUND Characteristics Providing New Key Insights into Physics and Performance of Silicon and Oxide Channel Ferroelectric FETs,” IEEE International Electron Devices Meeting (IEDM), pp. 32.4.1-32.4.4, Dec. 2022

  20. Han-Wen Hu, Wei-Chen Wang, Yuan-Hao Chang, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Ming Huang, Chong-Ying Lee, Tzu-Hsiang Su, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Chung-Kuang Chen, Han-Sung Chen, Hsiang-Pang Li, Tei-Wei Kuo, Meng-Fan Chang, Keh-Chung Wang, Chun-Hsiung Hung, and Chih-Yuan Lu, “ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration,” ACM International Symposium on Microarchitecture (MICRO), pp. 763-783, October 2022

  21. M. Y. Song, C. M. Lee1, S. Y. Yang, G. L. Chen, K. M. Chen, I J. Wang, Y. C. Hsin, K. T. Chang, C. F. Hsu1, S. H. Li, J. H. Wei, T. Y. Lee, M. F. Chang, X. Y. Bao, C. H. Diaz, and S. J. Lin, “High speed (1ns) and low voltage (1.5V) demonstration of 8Kb SOT-MRAM array,” 2022 Symposium on VLSI Technology (VLSI Symp.), pp. 377-378, June 2022

  22. H.-L. Chiang, J.-F. Wang, K.-H. Lin, C.-H. Nien1, J.-J. Wu, K.-Y. Hsiang4, C.-P. Chuu, Y.-W. Chen, X.W. Zhang, C. W. Liu, Tahui Wang, C.-C. Wang, M.-H. Lee, M.-F. Chang, C.-S. Chang, T.C. Chen, “Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array,” 2022 Symposium on VLSI Technology (VLSI Symp.), pp. 361-362, June 2022

  23. Han-Wen Hu, Wei-Chen Wang, Chung-Kuang Chen, Yung-Chun Lee, Bo-Rong Lin, Huai-Mu Wang, Yen-Po Lin, Yu-Chao Lin, Chih-Chang Hsieh, Chia-Ming Hu, Yi-Ting Lai, Han-Sung Chen, Yuan-Hao Chang, Hsiang-Pang Li, Tei-Wei Kuo, Keh-Chung Wang, Meng-Fan Chang, Chun-Hsiung Hung, Chih-Yuan Lu, “A 512Gb In-Memory-Computing 3D NAND Flash Supporting Similar Vector Matching Operations on AI Edge Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 138-140, Feb. 2022

  24. Tzu-Hsiang Hsu, Guan-Cheng Chen, Yi-Ren Chen, Chung-Chuan Lo, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang, Chih-Cheng Hsieh, “A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights using Mixed-mode Processing-in-Sensor Technique for Image Classification,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 1-3, Feb. 2022

  25. Samuel Spetalnick, Muya Chang, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury, “A 40nm 64kb 26.56 TOPS/W 2.37Mb/mm2 RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and > 75% use of Sensing Dynamic Range,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 1-3, Feb. 2022

  26. Muya Chang, Samuel Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury, “A 40nm 60.64TOPS/W ECC Capable Compute-in-Memory/Digital 2.25MB/768KKB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 1-3, Feb. 2022

  27. Win-San Khwa*, Yen-Cheng Chiu*, Chuan-Jia Jhang, Sheng-Po Huang, Chun-Ying Lee, Tai-Hao Wen, Fu-Chun Chang, Shao-Ming Yu, Tung-Yin Lee, Meng-Fan Chang, “A 40nm 2M-cell 8b-Precision Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5-65.0 TOPS/W for Tiny AI Edge Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 1-3, Feb. 2022

  28. Je-Min Hung, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Tai-Hao Wen, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang, “An 8Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4 TOPS/W - 21.6 TOPS/W for AI Edge Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 1-3, Feb. 2022

  29. Yen-Cheng Chiu, Win-San Khwa, Chia-Sheng Yang, Shih-Hsin Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang, “A 22nm 4Mb STT-MRAM data-encrypted Near-Memory-Computation Macro with 192GB/s Read-and-Decryption Bandwidth and 25.1- 55.1 TOPS/W at 8b MAC for AI-oriented Operations,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 1-3, Feb. 2022

  30. Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang, “A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with 6.6ns Latency 1241 GOPS and 37.01 TOPS/W for 8b-MAC Operations for Edge-AI Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 1-3, Feb. 2022

  31. Zhaofang Li, Syuan-Hao Sie, Jye-Luen Lee, Yi-Ren Chen, Ting-I Chou, Ping-Chun Wu, Yu-Ting Chuang, Yu-Te Lin, I-Cherng Chen, Chih-Cheng Lu, Ying-Zong Juang, Shih-Wen Chiu, Chih-Cheng Hsie, Meng-Fan Chang, Kea-Tiong Tang, “A Miniature Electronic Nose for Breath Analysis,” IEEE International Electron Devices Meeting (IEDM), pp. 35.2.1-35.2.4, Dec. 2021

  32. Y.-D. Chih, C.-C. Chou, Y.-C. Shih, C.-F. Lee,W.-S. Khwa, C.-Y. Wu, K.-H. Shen, W.-T Chu, M-F Chang, H. Chuang, T.-Y. J. Chang, “Design Challenges and Solutions of Emerging Nonvolatile Memory for Embedded Applications,” IEEE International Electron Devices Meeting (IEDM), pp. 2.4.1-2.4.4, Dec. 2021

  33. V. Pi-Ho Hu, C-J Liu, H-L Chiang, J-F Wang, C-C Cheng, T-C Chen, M-F Chang, “High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing,” IEEE International Electron Devices Meeting (IEDM), pp. 8.6.1-8.6.4, Dec. 2021

  34. H-L Chiang, J-J Wu, C-H Chou, Y-F Hsiao, Y-C Chen, L. Liu, J-F Wang, T-C Chen, P-JJun Liao, J. Cai, X. Bao, A. Cheng, M-F Chang, “Design Technology Co-Optimization for Cold CMOS Benefits in Advanced Technologies,” IEEE International Electron Devices Meeting (IEDM), pp. 13.2.1-13.2.4, Dec. 2021

  35. E. Ambrosi, C. H. Wu, H. Y. Lee, P. C. Chang, C. F. Hsu, C. M. Lee, C. C. Chang, Y. Y Chen, D. W. Heh, D. H. Hou, P. J. Liao, T. Y. Lee, M. F. Chang, H.-S. P. Wong, and X. Y. Bao, “Low variability high endurance and low voltage arsenic-free selectors based on GeCTe,” IEEE International Electron Devices Meeting (IEDM), pp. 28.5.1-28.5.4, Dec. 2021

  36. Xin Si, Yongliang Zhou, Jun Yang, Meng-Fan Chang, “Challenge and Trend of SRAM Based Computation-in-Memory Circuits for AI Edge Devices,” 2021 IEEE 14th International Conference on ASIC (ASICON), Oct. 2021

  37. Ruiqi Guo, Hao Li, Ruhui Liu, Zhixiao Zhang, Limei Tang, Hao Sun, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin, “A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation,” 2021 Symposium on VLSI Technology (VLSI Symp.), June 2021

  38. Linfang Wang, Wang Ye, Jinru Lai, Jing Liu, Jianguo Yang, Xin Si, Changxing Huo, Chunmeng Dou, Xiaoxin Xu, Qi Liu, Dashan Shang, Feng Zhang, Hangbing Lv, Meng-Fan Chang, Hiroshi Iwai, “A 14nm 100Kb 2T1R Transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme,” 2021 Symposium on VLSI Technology (VLSI Symp.), June 2021

  39. Ruiqi Guo, Hao Li, Ruhui Liu, Zhixiao Zhang, Limei Tang, Hao Sun, Leibo Liu, Meng-Fan Chang, Shaojun Wei, Shouyi Yin, “A 6.54-to-26.03 TOPS/W Computing-In-Memory RNN Processor using Input Similarity Optimization and Attention-based Context-breaking with Output Speculation,” 2021 Symposium on VLSI Circuits (VLSI Symp.), June 2021

  40. W.S. Khwa*, K. Akarvardar, …, Meng-Fan Chang, “MLC PCM Techniques to Improve Nerual Network Inference Retention Time by 105X and Reduce Accuracy Degradation by 10.8X,” Symposium on VLSI Technology (VLSI Symp.), June 2021

  41. H.L. Chiang, J.F. Wang, …, Meng-Fan Chang*, “Cold MRAM as a Density Booster for Embedded NVM in Advanced Technology,” Symposium on VLSI Technology (VLSI Symp.), June 2021

  42. C.H. Wu, C.M. Lee, …, Meng-Fan Chang, Xinyu Bao*, “Low-voltage (~1.3V), Arsenic Free Threshold Type Selector with Ultra High Endurance (> 1011) for High Density 1S1R Memory Array,” Symposium on VLSI Technology (VLSI Symp.), June 2021

  43. Massimo Giordano, Kartik Prabhu, …, Meng-Fan Chang, Priyanka Raina, “CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference,” Symposium on VLSI Circuits (VLSI Symp.), June 2021

  44. Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury*, “A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation,” IEEE Custom Integrated Circuits Conference (CICC ), pp. 1-2, 2021

  45. Yuxin Zhang, Sitao Zeng, Zhiguo Zhu, Zhaolong Qin, Chen Wang, Jingjing Li, Sanfeng Zhang, Yajuan He, Chunmeng Dou, Xin Si, Meng-Fan Chang, Qiang Li , “A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2021

  46. Linfang Wang, Wang Ye, Junjie An, Chunmeng Dou, Qi Liu, Meng-Fan Chang, Ming Liu, “Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile Computing-in-Memory Based on Resistive Memory,” IEEE International Symposium on Circuits and Systems (ISCAS), May 2021

  47. Chuan-Jia Jhang, Ping-Cheng Chen, Meng-Fan Chang*, “Challenges of Computation-in-Memory Circuits for AI Edge Applications,” 2021 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), pp. 1-2, April 2021

  48. Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li, Shih-Chieh Chang , Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 28nm 384Kb 6T SRAM Computation-in-memory Macro with 8b-precision for AI Edge Chips,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 250-251, Feb. 2021

  49. Cheng-Xin Xue, Je-Min Hung, Hui-Yao Kao, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Peng Chen, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*, “A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91-195.7 TOPS/W for Tiny AI Edge Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 246-247, Feb. 2021

  50. Yu-Der Chih, Po-Hao Lee, Hidehiro Fujiwara, Yi-Chun Shih, Chia-Fu Lee, Rawan Naous, Yu-Lin Chen, Chieh-Pu Lo, Cheng-Han Lu, Haruki Mori, Wei-Chang Zhao, Dar Sun, Mahmut E. Sinangil, Yen-Huei Chen, Tan-Li Chou, Kerem Akarvardar, Hung-Jen Liao, Yih Wang, Meng-Fan Chang, Tsung-Yung Jonathan Chang, “An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications,”IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 252-253, Feb. 2021

  51. Ruiqi Guo, Zhiheng Yue, Xin Si, Te Hu, Hao Li, Limei Tang, Yabing Wang, Leibo Liu, Meng-Fan Chang, Qiang Li, Shaojun Wei, Shouyi Yin*, “A 5.99-to-691.1 TOPS/W Tensor-train In-Memory-Computing Processor using Bit-Level Sparsity based Optimization and Variable-Precision Quantization,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 242-243, Feb. 2021

  52. Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hung, Meng-Fan Chang, Nan Sun, Xueqing Li, Huazhong Yang, Yongpan Liu*, “A 2.75-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 238-239, Feb. 2021

  53. Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury*, “A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute- in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 404-405, Feb. 2021

  54. Fu-Kuo Hsueh, Je-Min Hung, Sheng-Po Huang, Yen-Hsiang Huang, Cheng-Xin Xue, Chang-Hong Shen*, Jia-Min Shieh*, Wen-Cheng Chiu, Chao-Cheng Lin, Bo-Yuan Chen, Szu-Ching Liu, Shih-Wei Chen, Deng-Yan Niou, Wen-Hsien Huang, Kai-Shin Li, Kun-Kin Lin, Da-Chiang Chang, Kun-Ming Chen, Guo-Wei Huang, Ci-Ling Pan, Meng-Fan Chang*, Chenming Hu, Wen-Kuan Yeh, , “First Demonstration of Ultrafast Laser Annealed Monolithic 3D Gate-All-Around CMOS Logic and FeFET Memory with Near-Memory-Computing Macro,” IEEE International Electron Devices Meeting (IEDM), pp.28.5.1-28.5.4, Dec. 2020

  55. Akshay Krishna Ramanathan, Srivatsa Srinivasa Rangachar, Je-Min Hung, Chun-Ying Lee, Cheng-Xin Xue, ShengPo Huang, Fu-Kuo Hsueh, Chang-Hong Shen, Jia-Min Shieh, Wen-Kuan Yeh, Mon-Shu Ho, Hariram Thirucherai Govindarajan, Jack Sampson, Meng-Fan Chang* , Vijaykrishnan Narayanan, “Monolithic 3D+-IC Based Massively Parallel Compute-in-Memory Macro for Accelerating Database and Machine Learning Primitives,” IEEE International Electron Devices Meeting (IEDM), pp.40.4.1-40.4.4, Dec. 2020

  56. Jianguo Yang, Xiaoyong Xue, Xiaoxin Xu, Hangbing Lv, Feng Zhang, Xiaoyang Zeng, Meng-Fan Chang, Ming Liu, “A 28nm 1.5Mb Embedded 1T2R RRAM with 14.8 Mb/mm2 using Sneaking Current Suppression and Compensation Techniques,” Symposium on VLSI Circuits (VLSI Symp.), June 2020

  57. Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu, “A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2020

  58. C.-X. Xue..., M.-F. Chang*, “A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 244-245, Feb. 2020

  59. J.-W. Su..., M.-F. Chang*, “A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 240-241, Feb. 2020

  60. X. Si..., M.-F. Chang*, “A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 246-247, Feb. 2020

  61. T.-C. Chang..., M.-F. Chang*, “A 22nm 1Mb 1024b-Read and Near-Memory-Computing Dual-Mode STT-MRAM Macro with 42.6GB/s Read Bandwidth for Security-Aware Mobile Devices,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 224-225, Feb. 2020

  62. Jinshan Yue, Zhe Yuan, Xiaoyu Feng, Yifan He, Zhixiao Zhang, Xin Si, Ruhui Liu, Meng-Fan Chang, Xueqing Li, Huazhong Yang, Yongpan Liu*, “A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 234-235, Feb. 2020

  63. Tzu-Hsiang Hsu, Yen-Kai Chen, Jun-Shen Wu, Wen-Chien Ting, Cheng-Te Wang, Chen-Fu Yeh, Syuan-Hao Sie, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh*, “A 0.8V Multimode Vision Sensor for Motion and Saliency Detection with Ping-Pong PWM Pixel,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 110-111, Feb. 2020

  64. Qi Liu, Bin Gao, Peng Yao, Dong Wu, Junren Chen, Yachuan Pang, Wenqiang Zhang, Yan Liao, Cheng-Xin Xue, Wei-Hao Chen, Jianshi Tang, Yu Wang, Meng-Fan Chang, He Qian, Huaqiang Wu*, “A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 500-501, Feb. 2020

  65. T.-H. Hsu..., M.-F. Chang and C.-C. Hsieh*, “AI Edge Devices Using Computing-In-Memory and Processing-In-Sensor: From System to Device,” IEEE International Electron Devices Meeting (IEDM), pp. 530-533, Dec. 2019

  66. F.-K. Hsueh..., M.-F. Chang ..., and W.-K. Yeh*, “Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs,” IEEE International Electron Devices Meeting (IEDM), pp.54-57, Dec. 2019

  67. Z. Zhang..., M.-F. Chang*, “A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 217-218, Nov. 2019

  68. T.-H. Hsu..., M.-F. Chang and C.-C. Hsieh*, “A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction,” IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 33-36, Dec. 2019

  69. C.-X. Xue, M.-F. Chang*, “Challenges in Circuit Designs of Nonvolatile-memory based computing-in-memory for AI Edge Devices,” International SoC Design Conference (ISOCC), pp. 164-165, Oct. 2019

  70. X. Si..., M.-F. Chang*, “Circuit Design Challenges in Computing-in-Memory for AI Edge Devices,” IEEE 13th International Conference on ASIC (ASICON), Oct. 2019

  71. K.-T. Tang..., M.-F. Chang, “Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices,” IEEE Symposium on VLSI Circuits (VLSI Symp.), C166-C167, June, 2019

  72. Y.-C. Chiu..., M.-F. Chang* , “A 40nm 2Mb ReRAM Macro with 85% Reduction in FORMING Time and 99% Reduction in Page-Write Time Using Auto-FORMING and Auto-Write Schemes,” IEEE Symposium on VLSI Technology (VLSI Symp.), T232-T233, June, 2019

  73. B. Yan..., M.-F. Chang , and H Li*, “RRAM-based Spiking Nonvolatile Computing-In-Memory Processing Engine with Precision-Configurable In Situ Nonlinear Activation,” IEEE Symposium on VLSI Technology (VLSI Symp.), T86-T87, June, 2019

  74. S. Srinivasa..., M.-F. Chang* ,and V. Narayanan*, “Monolithic 3D+-IC Based Reconfigurable Compute-in-Memory SRAM Macro,” IEEE Symposium on VLSI Technology (VLSI Symp.), T32-T33, June, 2019

  75. R. Guo, …, M.-F. Chang, S. Wei, and S. Yin, “A 5.1pJ/Neuron 127.3us/Inference RNN-Based Speech Recognition Processor Using 16 Computing-in-Memory SRAM Macros in 65nm CMOS,” Symposium on VLSI Ciruits (VLSI Symp.), pp. C120-C121, June 2019 (THU accepted)

  76. C.-X. Xue, M.-F. Chang*, “A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing time for CNN-based AI Edge Processors,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 388-390, Feb. 2019

  77. X. Si, ., M.-F. Chang*, “A Twin-8T SRAM Computation-In-Memory Macro for Multiple-bits CNN-Based Machine Learning,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 396-398, Feb. 2019

  78. J. Yue, …M.-F. Chang, X. Li, H. Yang, Y. Liu*, “A 65nm 0.39-140.3 TOPS/W 1-12bit Unified Neural Network Processor Using Block-circulant Enabled Transpose-Domain Acceleration with 8.1x Higher TOPS/mm2 and 6T HBST-TRAM Based 2D Data Reuse Architecture,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 138-140, Feb. 2019

  79. Y. Pang, …, M.-F. Chang, H. Wu*, “A Reconfigurable RRAM Physical Unclonable Function Utilizing Post-Process Randomness Source with < 6E-6 Nature Bit Error Rate,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 402-404, Feb. 2019

  80. Fu-Kuo Hsueh, …, Vijaykrishnan Narayanan, Meng-Fan Chang*, and Wen-Kuan Yeh, “Ultra-Low Power 3D NC-FinFET-based Monolithic 3D+-IC with Computing-in-Memory for Intelligent IoT Devices,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 15.1.1-15.1.4, Dec. 2018

  81. Kai-Shin Li, Fu-Kuo Hsueh, Chang-Hong Shen, Jia-Min Shieh, Hsiu-Chih Chen, Wen-Hsien Huang, Hsiao-Yun Chiu, Chih-Chao Yang, Tung-Ying Hsieh, Bo-Yuan Chen, Wei-Hao Chen, Kuo-Hsiang Hsu, Meng-Fan Chang, Wen-Kuan Yeh, “FinFET-based Monolithic 3D+ with RRAM Array and Computing in Memory SRAM for Intelligent IoT Chip Application,” 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-3, 2018

  82. Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, “DL-RSIM: A Simulation Framework to Enable Reliable ReRAM-based Accelerators for Deep Learning ,” (ICCAD), pp. 1-8, 2018

  83. Pin-Yi Li, Cheng-Han Yang, Wei-Hao Chen, Jian-Hao Huang, Wei-Chen Wei, Je-Syu Liu, Wei-Yu Lin, Zu- Hsiang Hs, Chih-Cheng Hsieh, Ren-Shuo Liu, Meng-Fan Chang, Kea-Tiong Tang*, “A Neuromorphic Computing System for Bitwise Neural Networks Based on ReRAM Synaptic Array,” IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. xx-xx, 2018

  84. Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi and Meng-Fan Chang, “A 28nm 320Kb TCAM Macro with Sub-0.8ns Search Time and 3.5+x Improvement in Delay-Area-Energy Product using Split-Controlled Single-Load 14T Cell,” IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 127-128, Nov. 2018

  85. C. Dou, W.-H. Chen, C.-X. Xue, W.-Y. Lin, W.-E. Lin, J.-Y. Li, H.-T. Lin, and M.-F. Chang*, “Nonvolatile Circuits-Devices Interaction for Memory, Logic and Artificial Intelligence,” Symposium on VLSI Technology (VLSI Symp.), pp. 171-172, June 2018 (invited)

  86. Z. Yuan, J. Yue, H. Yang, Z. Wang, J. Li, Y. Yang, Q. Guo, X. Li, M.-F. Chang, H. Yang, Y. Liu*, “Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers,” Symposium on VLSI Circuits (VLSI Symp.), pp. 33-34, June 2018

  87. R. Liu, …, M.-F. Chang and S. Yu, “Parallelizing SRAM Arrays with Customized Bit-Cell for Binary Neural Networks,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2018

  88. Yixiong Yang, Zhibo Wang, Pei Yang, Meng-Fan Chang, Mon-Shu Ho, Huazhong Yang, Yongpan Liu , “A 2-GHz Direct Digital Frequency Synthesizer Based on LUT and Rotation,” 2018 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, 2018

  89. W.-H. Chen, …, M.-F. Chang*, “A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with sub-16ns Multiply-and-Accumulate for Binary DNN AI Edge Processors,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 494-495, Feb. 2018

  90. V. Khwa, …, M.-F. Chang*, “A 65nm 4Kb Algorithm-Dependent Computing-in-Memory SRAM Unit-Macro with 2.3ns and 55.8 TOPS/W Fully Parallel Product-Sum Operation for Binary DNN Edge Processors,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 496-497, Feb. 2018

  91. T.-H. Yang, …, M.-F. Chang*, “A 28nm 32Kb Embedded 2T2MTJ STT-MRAM Macro with 1.3ns Read-Access-Time for Fast and Reliable Read Applications,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 480-481, Feb. 2018

  92. W.-H. Chen, …, M.-F. Chang*, “A 16Mb Dual-Mode ReRAM Macro with Sub-14ns Computing-In-Memory and Memory Functions Enabled by Self-Write Termination Scheme,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 28.2.1-28.2.4, Dec. 2017

  93. F.-K. Hsueh, …, M.F. Chang, and W.-K. Yeh, “TSV-free FinFET-based Monolithic 3D+-IC with Computing-in-Memory SRAM Cell for Intelligent IoT Devices,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 12.6.1-12.6.4, Dec. 2017

  94. Feng Zhang, Dongyu Fan, Yuan Duan, Jin Li, Cong Fang, Yun Li, Xiaowei Han, Lan Dai, Chengying Chen, Jinshun Bi, Ming Liu, Meng-Fan Chang, “A 130nm 1Mb HfOx embedded RRAM macro using self-adaptive peripheral circuit system techniques for 1.6X work temperature range ,” 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 173-176, Nov. 2017

  95. M.-F. Chang, “Challenges of emerging memory and memristor based circuits: Nonvolatile logics, IoT security, deep learning and neuromorphic computing,” IEEE 12th International Conference on ASIC (ASICON), pp. 140-143, Oct. 2017 (Invited Talk/Paper)

  96. Srivatsa Rangachar Srinivasa, Karthik Mohan, Wei-Hao Chen, Kuo-Hsinag Hsu, Xueqing Li, Meng-Fan Chang, Sumeet Kumar Gupta, John Sampson, Vijaykrishnan Narayanan, “Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via,” 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp128-133, 2017

  97. C.-P. Lo, …, M.F. Chang*, “Embedded 2Mb ReRAM Macro with 2.6ns Read Access Time Using Dynamic- Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier for IoE Applications,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. C164-C165, June 2017

  98. F. Su, …, M.-F. Chang, H. Yang, Y. Liu, “A 462GOPs/J RRAM-Based Nonvolatile Intelligent Processor for Energy Harvesting IoE System Featuring Nonvolatile Logics and Processing-In-Memory,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. T260-T261, June 2017

  99. F. Su,…, M.-F. Chang, H. Yang, Y. Liu, “A 130nm FeRAM-Based Energy Harvesting Nonvolatile System-On-Chip with 5.2x Higher Performance & 26.9x Faster System Wakeup Using Adaptive Load Balance and Fast Peripheral Startup Schemes,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. C260-C261, June 2017

  100. W. H. Chen, .., M.-F. Chang*, “Circuit Design for Beyond Von Neumann Applications Using Emerging Memory: From Nonvolatile Logics to Neuromorphic Computing,” in Proc. International Symposium on Quality Electronic Design (ISQED), pp. 23-28 March 2017 (Invited Paper/special session)

  101. C.-P. Lo, W.-H. Chen, …, M.-F. Chang*, “A ReRAM-based Single-NVM Nonvolatile Flip-Flop with Reduced Stress-Time and Write-Power against Wide Distribution in Write-Time by Using Self-Write-Termination Scheme for Nonvolatile Processors in IoT Era,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 16.3.1-16.3.4, Dec. 2016

  102. Ra-Min Tain, Dyi-Chung Hu, Kai-Ming Yang, Yu-Hua Chen, Chih-Lun Wang, Cheng-Hsiung Wang, Ching Chang, Yan-bin Chang, Zih-Yu Ciou, Han-Wen Hu, Meng-Fan Chang, “SiP assembly and application using glass substrate with through vias,” 2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), pp. 281-284, 2016

  103. Fang Su, Zhibo Wang, Jinyang Li, Meng-Fan Chang, Yongpan Liu, “Design of nonvolatile processors and applications,” 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1-6, 2016

  104. M.-F. Chang, et al., “A sub-0.5V charge pump circuit for resistive RAM (ReRAM) enabled low supply voltage nonvolatile logics and nonvoaltile processors,” in Proc. IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 342-345, Aug. 2016 (invited)

  105. S. George, …, M.-F. Chang, …, V. Narayanan, “Nonvolatile Memory Design Based on Ferroelectric FETs,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2016

  106. M.-F. Chang, et al, “Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1142-1145, May 2016. (invited)

  107. M.-H. Kao, C,-C, Yang, …, M.-F. Chang, J.-M. Shieh, “A-SiGeC thin film photovoltaic enabled self-power monolithic 3D IC under indoor illumination,” in Proc. IEEE International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), pp. 1-2, April 2016

  108. C.-C. Lin, …, M.-F. Chang*, “A 256b-Wordlength ReRAM-based TCAM with 1ns Search-Time and 14x Improvement in WordLength-EnergyEfficiency-Density Product using 2.5T1R cell,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 136-137, Feb. 2016

  109. V. Khwa*, M.-F. Chang, …, “A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100X for Storage Class Memory Applications,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 134-135, Feb. 2016

  110. Y. Liu*, …, M.-F. Chang, and H. Yang, “A 65nm ReRAM-Enabled Nonvolatile Processor with 6X Reduction in Restore Time and 4X Higher Clock Frequency Using Adaptive Data Retention and Self-Write-Termination Nonvolatile Logic,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 84-85, Feb. 2016

  111. T.T. Wu, C.-H. Shen*, J.-M. Shieh*, …, M.-F. Chang, and W.-K. Yeh, “Low-Cost and TSV-free Monolithic 3D-IC with Heterogeneous Integration of Logic, Memory and Sensor Analogy Circuitry for Internet of Things,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 25.4.1-25.4.4, Dec. 2015

  112. A. Lee, M.-F. Chang*, et al., “ReRAM-based 7T1R Nonvolatile SRAM with 2x Reduction in Store Energy and 94x Reduction in Restore Energy for Frequent-Off Instant-On Applications,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 76-77, June 2015

  113. M.-F. Chang*, et al., “Supply-Variation-Resilient Nonvolatile 3D IC and 3D Memory Using Low Peak-Current On-Chip Charge-Pump Circuits,” in Proc. IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 118-121, June 2015 (Invited Talk/Paper)

  114. H.-J. Tsai, …, M.-F. Chang and T.-F. Chen*, “Energy-Efficient Non-Volatile TCAM Search Engine Design Using Priority-Decision in Memory Technology for DPI,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2015

  115. Y. P. Liu*, …, M.-F. Chang, …, et al., “Ambient Energy Harvesting Nonvolatile Processors: From Circuit to System,” in Proc. Design Automation Conference (DAC), pp. 1-6, June 2015

  116. A. Lee, C.-C. Lin, T.-C. Yang, and M.-F. Chang*, “An embedded ReRAM Using a Small-offset Sense Amplifier for Low-Voltage Operations,” in Proc. IEEE International Symposium on VLSI Design, Automation and Testing (VLSI-DAT), pp. 1-4, April 2015

  117. H. Li, Y. Liu*, Q. Zhao, Y. Gu, X. Sheng, G. Sun, C. Zhang, M.-F. Chang, R. Luo, and H. Z. Yang, “An energy efficient backup scheme with low inrush current for nonvolatile SRAM in energy harvesting sensor nodes,” in Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 7-12, March 2015

  118. M.-F. Chang*, C.-F. Chen, et al., “A 28nm 256Kb 6T-SRAM with 280mV Improvement in VMIN Using a Dual-Split-Control Assist Scheme,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 314-315, Feb. 2015

  119. M.-F. Chang*, C.-C. Lin, et al., “A 3T1R Nonvolatile TCAM Using MLC ReRAM with Sub-1ns Search Time,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 318-319, Feb. 2015

  120. M.-F. Chang*, et al., “Challenges at Sensing Circuits for Resistive Memory and Memristor-based Nonvolatile Logics,” in Proc. 2014 IEEE Asia South Pacific Design Automation Conference (ASP-DAC), pp. 569 – 574, Jan. 2015 (Invited Talk/Paper) (Tokyo, Japan)

  121. C.-H. Shen, J.-M. Shieh, W.-H. Huang, T.-T. Wu, C.-F. Chen, M.-H. Kao, C.-C. Yang, C.-D. Lin, H.-H. Wang, T.-Y. Hsieh, B.-Y. Chen, G.-W. Huang, M.-F. Chang, and F.-L. Yang, “Heterogeneously integrated sub-40nm low-power epi-like Ge/Si monolithic 3D-IC with stacked SiGeC ambient light harvester,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 3.6.1-3.6.4, Dec. 2014

  122. W. S. Khwa, J.Y. Wu, T.H. Su, H. P. Li, M. BrightSky, T. Y. Wang, T. H. Hsu, P. Y. Du, R. Cheek, E. K. Lai, Y. Zhu, M.H. Lee, M. F. Chang, H.L. Lung, and C. Lam, “Novel Inspection and Annealing Procedure to Rejuvenate Phase Change Memory from Cycling-Induced Degradations for Storage Class Memory Applications,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 29.8.1-29.8.4, Dec. 2014

  123. M.-F. Chang*, C.-W. Wu, J.-Y. Hung, Y.-C. King, and C.-J. Lin, M.-S. Ho, C.-C. Kuo and S.-S. Sheu, “A Low-Power Subthreshold-to-Superthreshold Level-Shifter for Sub-0.5V Embedded Resistive RAM (ReRAM) Macro in Ultra Low-Voltage Chips,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 695-698, Oct. 2014 (Best Paper Award)

  124. W.-P. Lin, S.-S. Sheu, C.-C. Kuo, P.-L. Tseng, M.-F. Chang, K.-L. Su, C.-S. Lin, K.-H. Tsai, S.-H. Lee, S.-C. Liu, Y.-S. Chen, H.-Y. Lee, C.-C. Hsu, F.T. Chen, T.-K. Ku, M.-J. Tsai, and M.-J. Kao, “A nonvolatile look-up table using ReRAM for reconfigurable logic,” in Proc. IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 133-136, Nov. 2014

  125. M.-F. Chang*, Albert Lee, C.-C. Kuo, S.-Shyuan Sheu, Fredrick. T Chen, Tzu-Kun Ku, Yong-Pan Liu, Hua-Zhong Yang, Ping-Cheng Chen, “Challenges at Circuit Designs for Resistive-Type Nonvolatile Memory and Nonvolatile Logics in Mobile and Cloud Applications,” in Proc. IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), pp. 1-4, Oct. 2014 (Invited Talk/Paper)

  126. L.-Y. Huang, M.-F. Chang*, C.-H. Chuang, C.-C. Kuo, C.-F. Chen, G.-H. Yang, H.-J. Tsai, T.-F. Chen, S.-S. Sheu, K.-L. Su, F.T. Chen, T.-K. Ku, M.-J. Tsai, M.-J. Kao, “ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 122-123, June 2014 (Hawaii, US)

  127. Hsiang-Jen Tsai, Chien-Chih Chen, Keng-Hao Yang, Ting-Chin Yang, Li-Yue Huang, Ching-Hao Chung, Meng-Fan Chang and Tien-Fu Chen*, “Leveraging Data Lifetime for Energy-aware Last Level Non-Volatile SRAM Caches using Redundant Store Elimination,” in Proc. IEEE Design Automation Conference (DAC), pp. 1-6, June 2014

  128. M.-F. Chang*, J.-J. Wu, T.-F. Chien, Y.-C. Liu, T.-C. Yang, W.-C. Shen, Y.-C. King, C.-J. Lin, K.-F. Lin, Y.-D. Chih, S. Natarajan, and J. Chang, “Embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V Read Using Swing-Sample-and-Couple Sense Amplifier and Self-Boost-Write-Termination Scheme,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 332-333, Feb. 2014

  129. K. T. Tang*, S-W. Chiu, C-H. Shih, C-L. Chang, C-M. Yang, D-J. Yao, J-H. Wang, C-M. Huang, H. Chen, K-H. Chang, C-C. Hsieh, T-H. Chang, M-F. Chang, C-M. Wang, Y-W. Liu, T-J. Chen, C-H. Yang, H. Chiueh, J-M. Shyu, et al., “A 0.5V 1.27mW Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 420-421, Feb. 2014

  130. C.-H. Shen*, J.-M. Shieh, W.-H. Huang, T.-T. Wu, B.-Y. Chen, G.-W. Huang, Y.-C. Lien, C.-F. Chen, M.-F. Chang, C. Hu, and F.-L. Yang, “Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 232 – 235, Dec. 2013

  131. Yen-Cheng Liu, Meng-Fan Chang*, Yu-Fan Lin, Jui-Jen Wu, Che-Ju Yeh, Shin-Jang Shen, Ping-Cheng Chen, Wu-Chin Tsai, Yu-Der Chih, Sreedhar Natarajan, “An Embedded Flash Macro with Sub-4ns Random-Read-Access Using Asymmetric-Voltage- Biased Current-Mode Sensing Scheme,” in Proc. IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 241-244, Nov. 2013 (Singapore)

  132. S.-S. Sheu*, C.-C. Kuo, M.-F. Chang, P.-L. Tseng, et al., “A ReRAM Integrated 7T2R Non-volatile SRAM for Normally-off Computing Application,” in Proc. IEEE Asia Solid-State Circuits Conference (A-SSCC), pp. 245-248, Nov. 2013 (Singapore)

  133. M.-F. Chang*, et al., “Area-Efficient Embedded RRAM Macros with Sub-5ns Random-Read-Access-Time Using Logic-Process Parasitic-BJT-Switch (0T1R) Cell and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 112-113, June 2013 (Kyoto, Japan)

  134. C.-H. Hung*, Y.-S. Yang, Y.-J. Kuo, T.-N. Lai, S.-J. Shen, J.-Y. Hsu, S.-N. Hung, H.-T. Lue, M.-F. Chang*, Y.-H. Shih, S.-L. Huang, T.-W. Chen, T. S. Chen, C. K. Chen, C.-Y. Hung, and C.-Y. Lu, “3D Stackable Vertical-Gate BE-SONOS NAND Flash with Layer-Aware Program-and-Read Schemes and Wave-Propagation Fail-Bit-Detection against Cross-Layer Process Variations,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 20-21, June 2013 (Kyoto, Japan)

  135. C. F. Chen, T.-H. Chang, L.-F. Chen, M.-F. Chang*, and H. Yamauchi, “A 210mV 7.3MHz 8T SRAM with Dual Data-Aware Write-Assists and Negative Read Wordline for High Cell-Stability, Speed and Area-Efficiency,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 130-131, June 2013 (Kyoto, Japan)

  136. M. B. Chen, L.F. Chen, M.-F. Chang*, S.-M. Yang, Y.-J. Kuo, J.-J. Wu, M.-S. Ho, H.-Y. Su, Y.-H. Chu, W.-C. Wu, T.-Y. Yang, and H. Yamauchi, “A 260mV L-shaped 7T SRAM with Bit-Line (BL) Swing Expansion Schemes Based on Boosted BL, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 112-113, June 2012 (Hawaii, US)

  137. M.-F. Chang*, C.-W. Wu, C.-C. Kuo, S.-J. Shen, S.-M. Yang, K.-F. Lin, Y.-C. King, C.-J. Lin, and Y.-D. Chih, “A 0.5V 4Mb Logic-Process Compatible Embedded Resistive RAM (ReRAM) in 65nm CMOS Using Low Voltage Current-Mode Sensing Scheme with 45ns Random Read Time,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 434-435, Feb. 2012

  138. K.-T. Tang*, S.-W. Chiu, M.-F. Chang, C.-C. Hsieh, and J. M. Shyu, “A wearable Electronic Nose SoC for healthier living,” 2011 IEEE Biomedical Circuits and Systems Conference (BioCAS), pp. 293-296, Nov. 2011

  139. M.-F. Chang*, et al., “Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM),” in Proc. IEEE International Conference on ASIC (ASICON), pp. 299-302, Oct. 2011

  140. M.-F. Chang*, W.-C. Wu, C.-S. Lin, P.-F. Chiu, M.-B. Chen, Y.-H. Chen, H.-C. Lai, Z.-H. Lin, S.-S. Sheu, T.-K. Ku, and H. Yamauchi, “A Larger Stacked Layer Number Scalable TSV-based 3D-SRAM for High-Performance Universal-Memory-Capacity 3D-IC Platforms,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 74-75, June 2011 (Kyoto, Japan)

  141. Y.-H. Chen*, S.-Y. Chou, Q. Lee, W.-M. Chan, D. Sun, H.-J. Liao, P. Wang, M.-F. Chang, and H. Yamauchi, “A 40nm Fully Functional SRAM with BL Swing and WL Pulse Measurement Scheme for Eliminating a Need for Additional Sensing Tolerance Margins,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 70-71, June 2011 (Kyoto, Japan)

  142. M.-F. Chang*, S.-J. Shen, C.-C. Liu, C.-W. Wu, Y.-F. Lin, S.-C. Wu, C.-E. Huang, H.-C. Lai, Y.-C. King, C.-J. Lin, H.-J. Liao, Y.-D. Chih, H. Yamauchi, “An offset tolerant current-sampling-based sense amplifier for sub-100nA-cell-current nonvolatile memory,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 206-207, Feb 2011

  143. S.-S. Sheu, M.-F. Chang*, K.-F. Lin, C.-W. Wu, Y.-S. Chen, P.-F. Chiu, C.-C. Kuo, Y.-S. Yang, P.-C. Chiang, W.-P. Lin, C.-H. Lin, H.-Y. Lee, P.-Y. Gu, S.-M. Wang, F. T. Chen, K.-L. Su, C.-H. Lien, K.-H. Cheng, H.-T. Wu, T.-K. Ku, M.-J. Kao, and M.-J. Tsai, “A 4Mb embedded SLC Resistive-RAM macro with 7.2ns read-write random access time and 160ns MLC-access capability,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 200-201, Feb 2011

  144. C.-H. Wang, Y.-H. Tsai, K.-C. Lin, M.-F. Chang, Y.-C. King, C. J. Lin*, S.-S. Sheu, Y.-S. Chen, H.-Y. Lee, F. T. Chen, and M.-J. Tsai, “3-Dimensional 4F2 ReRAM Cell with CMOS Logic Compatible Process,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp. 29.6.1-29.6.4, Dec. 2010

  145. P.-F. Chiu, M.-F. Chang*, S.-S. Sheu, K.-F. Lin, P.-C. Chiang, C.-W. Wu, W.-P. Lin, C.-H. Lin, C.-C. Hsu, F.T. Chen, K.-L. Su, M.-J. Kao, M.-J. Tsai, “A Low Store Energy, Low VDDmin, Nonvolatile 8T2R SRAM with 3D Stacked RRAM Devices for Low Power Mobile Applications,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 229-230, June 2010 (Hawaii, US)

  146. J.-J. Wu, Y.-H. Chen, M.-F. Chang*, P.-W. Chou, Ch.-Y. Chen, H.-J., Liao, M.-B. Chen, Y.-H. Chu, W.-C. Wu, and H. Yamauchi, “A Large σVTH/VDD Tolerant Zigzag 8T SRAM with Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 103-104, June 2010 (Hawaii, US)

  147. M.-F. Chang*, S.-M. Yang, C.-W. Liang, C.-C. Chiang, P.-F. Chiu, K.-F. Lin, Y.-H. Chu, W.-C. Wu, and H. Yamauchi, “A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp. 266-267, Feb 2010 (San Francisco, US)

  148. M.-F. Chang*, J.-J. Wu, K.-T. Chen, and H. Yamauchi, “A differential data aware power-supplied (D2AP) 8T SRAM cell with expanded write/read stabilities for lower VDDmin applications,” Symposium on VLSI Circuits Dig. Tech. Papers (VLSI Symp.), pp. 156-157, June 2009 (Kyoto, Japan)

  149. M.-F. Chang*, S.-M. Yang, K.-T. Chen, H.-J. Liao and R. Lee, “Improving the speed and power of compilable SRAM using dual-mode self-timed technique,” in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), pp. 57-60, Dec. 2007

  150. M.-F. Chang*, D.-M. Kwai, S.-M. Yang, Y.-F. Chou, and P.-C. Chen, “Experiments on reducing standby current for compilable SRAM using hidden clustered source line control,” in Proc. IEEE International Conference on ASIC (ASICON), pp. 1038-1041, Oct. 2007

  151. D.-M. Kwai*, Y.-F. Chou, M.-F. Chang, et al., “FlexiVia ROM Compiler Programmable on Different Via Layers Based on Top Metal Assignment,” in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), pp. 28-33, Aug. 2006

  152. M.-F. Chang*, D.-M. Kwai, and K.-A. Wen, “Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique,” in Proc. IEEE International Workshop on Memory Technology, Design, and Testing (MTDT), pp. 16-21, Aug. 2005

  153. M.-F. Chang*, L.-Y. Chiou, and K.-A. Wen, “A low supply noise content sensitive ROM architecture for SoC,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 1021-1024, Dec. 2004

  154. M.-F. Chang*, K.-A. Wen and D.-M. Kwai, “Supply and substrate noise tolerance using dynamic tracking clusters in configurable memory designs,” in Proc. IEEE Int’l Symp. Quality Electronic Design (ISQED), pp. 297-302, Mar. 2004 (Oral)