Publications
Journal Papers (期刊論文)
Kartik Prabhu, Robert M Radway, Jeffrey Yu, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina, “MINOTAUR: A Posit-Based 0.42–0.50-TOPS/W Edge Transformer Inference and Training Accelerator,” IEEE Journal of Solid-State Circuits (JSSC), March 2025
Win-San Khwa, Tai-Hao Wen, Hung-Hsi Hsu, Wei-Hsing Huang, Yu-Chen Chang, Ting-Chien Chiu, Zhao-En Ke, Yu-Hsiang Chin, Hua-Jin Wen, Wei-Ting Hsu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Ashwin Sanjay Lele, Shih-Hsin Teng, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang, “A mixed-precision memristor and SRAM compute-in-memory AI processor,” (Nature), May 2025
Jinshan Yue, Yongpan Liu, Xiaoyu Feng, Yifan He, Jingyu Wang, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hong, Meng-Fan Chang, Nan Sun, Chunmeng Dou, Xueqing Li, Ming Liu, Huazhong Yang, “An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update,” IEEE Journal of Solid-State Circuits (JSSC), vol. 59, Issue. 5, pp. 1612-1627, May 2024
Yi Huang, Takashi Ando, Abu Sebastian, Meng-Fan Chang, J. Joshua Yang, Qiangfei Xia, “Memristor-based hardware accelerators for artificial intelligence,” Nature Reviews Electrical Engineering, pp. 1-14, Apr. 2024
Tai-Hao Wen, Je-Min Hung, Wei-Hsing Huang, Chuan-Jia Jhang, Yun-Chen Lo, Hung-Hsi Hsu, Zhao-En Ke, Yu-Chiao Chen, Yu-Hsiang Chin, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang “Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing,”Science, ,vol. 384, no. 6693, pp. 325-332, Apr. 2024
Akash Levy, Luke R Upton, Michael D Scott, Dennis Rich, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Boris Murmann, Priyanka Raina “EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage,” IEEE Journal of Solid-State Circuits (JSSC), Early Access, Apr. 2024
Xiaoyu Sun, Weidong Cao, Brian Crafton, Kerem Akarvardar, Haruki Mori, Hidehiro Fujiwara, Hiroki Noguchi, Yu-Der Chih, Meng-Fan Chang, Yih Wang, Tsung-Yung Jonathan Chang, “Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, issue 4, pp. 1191-2005, Apr, 2024
Fernando Aguirre, Abu Sebastian, Manuel Le Gallo, Wenhao Song, Tong Wang, J. Joshua Yang, Wei Lu, Meng-Fan Chang, Daniele Ielmini, Yuchao Yang, Adnan Mehonic, Anthony Kenyon, Marco A. Villena, Juan B. Roldán, Yuting Wu, Hung-Hsi Hsu, Nagarajan Raghavan, Jordi Suñé, Enrique Miranda, Ahmed Eltawil, Gianluca Setti, Kamilya Smagulova, Khaled N. Salama, Olga Krestinskaya, Xiaobing Yan, Kah-Wee Ang, Samarth Jain, Sifan Li, Osamah Alharbi, Sebastian Pazos & Mario Lanza, “Hardware implementation of memristor-based artificial neural networks,” Nature Communications, vol. 15, pp. 1974, Mar. 2024
Yen-Wen Chen, Rui-Hsuan Wang, Yu-Hsiang Cheng, Chih-Cheng Lu, Meng-Fan Chang, Kea-Tiong Tang, “SUN: Dynamic Hybrid-Precision SRAM-Based CIM Accelerator With High Macro Utilization Using Structured Pruning Mixed-Precision Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Early Access, Jan. 2024
De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chi-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang, “An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices,” IEEE Journal of Solid-State Circuits (JSSC), vol. 59, issue 1, pp. 219-230, Jan. 2024
Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, M.-F. Chang, “A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips,” IEEE Journal of Solid-State Circuits (JSSC), vol. 59, issue 1, pp. 196-207, Jan. 2024
Hung-Hsi Hsu, Tai-Hao Wen, Wei-Hsing Huang, Win-San Khwa, Yun-Chen Lo, Chuan-Jia Jhang, Yu-Hsiang Chin, Yu-Chiao Chen, Chung-Chuan Lo, Ren-Shuo Liu, Kea-Tiong Tang, Chih-Cheng Hsieh, Yu-Der Chih, Tsung-Yung Jonathan Chang, M.-F. Chang, “A Nonvolatile AI-Edge Processor With SLC–MLC Hybrid ReRAM Compute-in-Memory Macro Using Current–Voltage-Hybrid Readout Scheme,” IEEE Journal of Solid-State Circuits (JSSC), vol. 59, issue 1, pp. 116-127, Jan. 2024
Ashwin Sanjay Lele, Muya Chang, Samuel D Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury, “A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking,” IEEE Journal of Solid-State Circuits (JSSC), vol. 59, issue 1, pp. 52-64, Jan. 2024
Samuel D. Spetalnick, Muya Chang, Shota Konno, Brian Crafton, Ashwin Sanjay Lele, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury, “A 40-nm Compute-in-Memory Macro With RRAM Addressing IR Drop and Off-State Current,” IEEE Solid-State Circuits Letters, vol. 7, pp. 10-13 Dec. 2023
Tzu-Hsiang Hsu, Guan-Cheng Chen, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh, “A 0.8 V intelligent vision sensor with tiny convolutional neural network and programmable weights using mixed-mode processing-in-sensor technique for image classification,” IEEE Journal of Solid-State Circuits (JSSC), vol. 58, issue 11, pp. 3266-3274, Nov. 2023
Ruiqi Guo, Zhiheng Yue, Xin Si, Hao Li, Te Hu, Limei Tang, Yabing Wang, Hao Sun, Leibo Liu,“TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization,” IEEE Journal of Solid-State Circuits (JSSC), vol. 58, No. 3, pp. 852 - 866, Aug. 2023
Min-Yang Chiu, Guan-Cheng Chen, Tzu-Hsiang Hsu, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh, “A Multimode Vision Sensor With Temporal Contrast Pixel and Column-Parallel Local Binary Pattern Extraction for Dynamic Depth Sensing Using Stereo Vision,” IEEE Journal of Solid-State Circuits (JSSC), vol. 58, No. 10, pp. 2767 - 2777, July 2023
Yen-Cheng Chiu, Win-San Khwa, Chia-Sheng Yang, Shih-Hsin Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang, “A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices,” Nature Electronics, vol. 6, pp. 534 - 543, July 2023
Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang, “8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips,”IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 58, issue 3, pp. 877-892, Mar. 2023
Je-Min Hung, Tai-Hao Wen, Yen-Hsiang Huang, Sheng-Po Huang, Fu-Chun Chang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang*, “ 8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices,” IEEE Journal of Solid-State Circuits (JSSC), vol. 58, No. 1, pp. 303 - 315, Jan. 2023
Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien;Peng-I Mei;Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips ,”IEEE Journal of Solid-State Circuits (JSSC), vol. 58, No. 3, pp. 877 - 892, Sep. 2022
Jinshan Yue, Yongpan Liu, Zhe Yuan, Xiaoyu Feng,Yifan He, Wenyu Sun, Zhixiao Zhang, Xin Si, Ruhui Liu, Zi Wang, Meng-Fan Chang, Chunmeng Dou, Xueqing Li, Ming Liu, Huazhong Yang*, “STICKER-IM: A 65 nm Computing-in-Memory NN Processor Using Block-Wise Sparsity Optimization and Inter/Intra-Macro Data Reuse,” IEEE Journal of Solid-State Circuits (JSSC), vol. 57, No. 8, pp. 2560 - 2573, Aug. 2022
Yen-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Chieh-Pu Lo, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, Yier Jin, Meng-Fan Chang, “A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 57, No. 6, pp. 1936-1949, June 2022
Syuan-Hao Sie, Jye-Luen Lee, Yi-Ren Chen, Zuo-wei Yeh, Zhaofang Li, Chih-Cheng Lu, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang*, “MARS: Multi-macro Architecture SRAM CIM-Based Accelerator with Co-designed Compressed Neural Networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, No. 5, pp. 1550 - 1562, May 2022
K. Prabhu, A.Gural, Z.F. Khan, R.M. Radway, M. Giordano, K. Koul, R. Doshi, J.W. Kustin, T. Liu, G.B. Lopes, V. Turbiner, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, G. Lallement, B. Murmann, S. Mitra, P. Raina, “CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 57, No. 4, pp. 1013-1026, April 2022
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury, “A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 57, No. 3, pp. 845-857, March 2022
Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang, “Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 57, No. 2, pp. 609-624, Feb. 2022
Jong-Hyeok Yoon, Muya Chang, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury, “A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 57, No. 1, pp. 68-79, Jan. 2022
Je-Min Hung, Cheng-Xin Xue, Hui-Yao Kao, Yen-Hsiang Huang, Fu-Chun Chang, Sheng-Po Huang, Ta-Wei Liu, Chuan-Jia Jhang, Chin-I Su, Win-San Khwa, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Chung-Cheng Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang & Meng-Fan Chang, “A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices,”Nature Electronics 4, pp.921-930 , Dec. 2021
Haitong Li, Wei-Chen Chen, Akash Levy, Ching-Hua Wang, Hongjie Wang, Po-Han Chen, Weier Wan, Win-San Khwa, Harry Chuang, Y.-D. Chih, Meng-Fan Chang, H.-S. Philip Wong, Priyanka Raina, “SAPIENS: A 64-kb RRAM-Based Non-Volatile Associative Memory for One-Shot Learning and Inference at the Edge,” IEEE Transactions on Electron Devices (TED), Vol. 68, No. 12, pp. 6637-6643, Dec. 2021
Je-Min Hung, Chuan-Jia Jhang, Ping-Chun Wu, Yen-Cheng Chiu, Meng-Fan Chang, “Challenges and Trends of Nonvolatile In-Memory-Computation Circuits for AI Edge Devices,” IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS), Vol. 1, pp. 171-183, Oct. 2021
Xuehong Wang, Linfang Wang, Ye Wang, Junjie An, Chunmeng Dou, Zuheng Wu, Xumeng Zhang, Jing Liu, Chenggao Zhang, Zhihong Yao, Zhaoan Yu, Tuo Shi, Chixiao Chen, Xiping Jiang, Meng-Fan Chang, Qi Liu, “A 4T2R RRAM Bit Cell for Highly Parallel Ternary Content Addressable Memory,” IEEE Transactions on Electron Devices (TED), Vol. 68, No. 10, pp. 4933-4937, Oct. 2021
Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Yen-Lin Chung, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li, Meng-Fan Chang, “A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 56, No. 9, pp. 2817-2831, Sep. 2021
Tzu-Hsiang Hsu, Yen-Kai Chen, Min-Yang Chiu, Guan-Cheng Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh, “A 0.8 V Multimode Vision Sensor for Motion and Saliency Detection With Ping-Pong PWM Pixel,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 56, No. 8, pp. 2516-2524, Aug. 2021
Akshay Krishna Ramanathan, Hariram Thirucherai Govindarajan, Je-Min Hung, Chun-Ying Lee, Cheng-Xin Xue, Sheng-Po Huang, Fu-Kuo Hsueh, Chang-Hong Shen, Jia-Min Shieh, Wen-Kuan Yeh, Mon-Shu Ho, Jack Sampson, Meng-Fan Chang, Vijaykrishnan Narayanan, “CiM3D: Comparator-in-Memory Designs Using Monolithic 3-D Technology for Accelerating Data-Intensive Applications,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 7, No. 1, pp. 79-87, June 2021
Tzu-Hsiang Hsu, Yi-Ren Chen, Ren-Shuo Liu, Chung-Chuan Lo, Kea-Tiong Tang, Meng-Fan Chang, Chih-Cheng Hsieh, “A 0.5-V Real-Time Computational CMOS Image Sensor With Programmable Kernel for Feature Extraction,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 56, No. 5, pp. 1588-1596, May 2021
Bohan Lin, Yachuan Pang, Bin Gao, Jianshi Tang, Dong Wu, Ting-Wei Chang, Wei-En Lin, Xiaoyu Sun, Shimeng Yu, Meng-Fan Chang, He Qian, Huaqiang Wu, “A Highly Reliable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 56, No. 5, pp. 1641-2021, May 2021
Chuan-Jia Jhang, Cheng--Xin Xue, Je-Min Hung, Fu-Chun Chang, Meng-Fan Chang, “Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices,” IEEE Transactions on Circuits and Systems I (TCAS-I), Vol. 68, No. 5, pp. 1773-1786, May 2021
Linfang Wang, Wang Ye, Chunmeng Dou, Xin Si, Xiaoxin Xu, Jing Liu, Dashan Shung, Jianfeng Gao, Meng-Fan Chang, “Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control,” IEEE Transactions on Circuits and Systems II (TCAS-II), Vol. 68, No. 5, pp. 1640-1644, May 2021
Cheng-Xin Xue, Yen-Cheng Chiu, Ta-Wei Liu, Tsung-Yuan Huang, Je-Syu Liu, Ting-Wei Chang, Hui-Yao Kao, Jing-Hong Wang, Shih-Ying Wei, Chun-Ying Lee , Sheng-Po Huang, Je-Min Hung, Shih-Hsih Teng, Wei-Chen Wei, Yi-Ren Chen, Tzu-Hsiang Hsu, Yen-Kai Chen , Yun-Chen Lo, Tai-Hsing Wen, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Mon-Shu Ho, Chin-Yi Su, Chung-Cheng Chou, Yu-Der Chih, Meng-Fan Chang*, “A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices,” Nature Electronics, Vol. 4, pp. 81-90, Jan. 2021 (Research Article)
Yue Xi, Bin Gao, Jianshi Tang, An Chen, Meng-Fan Chang, Xiaobo Sharon Hu, Jan Van Der Spiegel, He Qian, Huaqiang Wu, “In-memory Learning with Analog Resistive Switching Memory: A Review and Perspective,” Proceedings of the IEEE, Vol. 109, No. 1, pp. 14-42, Jan. 2021
Yen-Cheng Chiu, Zhixiao Zhang, Jia-Jing Chen, Xin Si, Ruhui Liu, Yung-Ning Tu, Jian-Wei Su, Wei-Hsing Huang, Jing-Hong Wang, Wei-Chen Wei, Je-Min Hung, Shyh-Shyuan Sheu, Sih-Han Li, Chih-I Wu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang*, “A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 10, pp. 2790-2800, Oct. 2020
Wenqiang Zhang, Bin Gao, Jianshi Tang, Peng Yao, Shimeng Yu, Meng-Fan Chang, Hoi-Jun Yoo, He Qian, Huaqiang Wu, “Neuro-inspired computing chips,” Nature Electronics, Vol. 3, pp. 371-382, July 2020 (Review Article)
Wei-Chen Wei, Chuan-Jia Jhang, Yi-Ren Chen, Cheng-Xin Xue, Syuan-Hao Sie, Jye-Luen Lee, Hao-Wen Kuo, Chih-Cheng Lu, Meng-Fan Chang, Kea-Tiong Tang*, “A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random-Access Memory (ReRAM)-based Computing-In-Memory,” IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, Vol. 6, No. 1, pp. 45-52, July 2020
Je-Min Hung, Xueqing Li, Juejian Wu, and Meng-Fan Chang*, “Challenges and Trends in Developing Nonvolatile Memory-Enabled Computing Chips for Intelligent Edge Devices,” IEEE Transactions on Electron Devices (TED), Vol. 67 Issue 4, pp. 1444-1453, April 2020
C.-X. Xue..., M.-F. Chang*, “Embedded 1-Mb ReRAM-Based Computing-in-Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 1, pp. 203-215, Jan. 2020
X. Si..., M.-F. Chang*, “A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 1, pp. 189-202, Jan. 2020
X. Si..., M.-F. Chang*, “A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro with Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors,” IEEE Transactions on Circuits and System–I: Regular Papers (TCAS-I), Vol. 66, No. 11, pp. 4172-4185, Nov. 2019
Zhixiao Zhang, Xin Si, Srivatsa Srinivasa, Akshay Krishna Ramanathan, Meng-Fan Chang*, “Recent Advances in Compute-in-Memory Support for SRAM Using Monolithic 3-D Integration,” IEEE Micro, Vol. 39, No. 6, pp. 28-37, Nov. 2019
C.-X. Xue..., M.-F. Chang*, “A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 10, pp. 2743-2753, Oct. 2019
W.-H. Chen..., M.-F. Chang*, “CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors,” Nature Electronics, Vol. 2, No. 9, pp. 420-428, Sep. 2019 (Research Article)
B. Yan..., M.-F. Chang*, Y. Chen*, and H. Li*, “Resistive Memory‐Based In‐Memory Computing: From Device and Large‐Scale Integration System Perspectives,” Wiley Online Library: Advanced Intelligent Systems, Vol. 1, No. 7, pp. 1900068 1 16 , Aug 2019
Srivatsa Srinivasa, Akshay Krishna Ramanathan, Xueqing Li, Wei-Hao Chen, Sumeet Kumar Gupta, Meng-Fan Chang, Swaroop Ghosh, Jack Sampson, Vijaykrishnan Narayanan, “ROBIN: Monolithic-3D SRAM for Enhanced Robustness With In-MemoryComputation Support,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, No. 7, pp. 2533-2545, July 2019
Yiming Wang, Yun Li, Haihua Shen, Dongyu Fan, Dongyu Fan, Wei Wang, Ling Li, Qi Liu, Feng Zhang, Xinghua Wang, Meng-Fan Chang, Ming Liu, “A Few-Step and Low-Cost Memristor Logic based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 66, No. 4, pp. 662-666, April 2019
Chieh-Pu Lo, Wen-Zhang Lin, Wei-Yu Lin, Huan-Ting Lin, Tzu-Hsien Yang, Yen-Ning Chiang, Ya-Chin King, Chrong-Jung Lin, Yu-Der Chih, Tsung-Yung Jonathon Chang, and Meng-Fan Chang*, “ A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme against Resistance and Write-Delay Variation,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 2, pp. 584-595, Feb. 2019
He Zhang, Wang Kang, Youguang Zhang, Meng-Fan Chang, Weisheng Zhao*, “A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM ,” IEEE Access, pp. 64250-64260, Oct. 2018
Ting-I Chou, Kwuang-Han Chang, Jia-Yin Jhang, Shih-Wen Chiu, Guoxing Wang, Chia-Hsiang Yang, Herming Chiueh, Hsin Chen, Chih-Cheng Hsieh, Meng-Fan Chang, Kea-Tiong Tang*, “A 1-V 2.6-mW Environmental Compensated Fully Integrated Nose-on-a-Chip,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 65, No. 10, pp. 1365-1369, Oct. 2018
Wei-Hao Chen, Chien-Fu Chen, Yi-Ju Chen, Hsiao-Yun Chiu, Chang-Hong Shen, Jia-Min Shieh, Fu-Kuo Hsueh, Chih-Chao Yang, Bo-Yuan Chen, Guo-Wei Huang, Kai-Shin Li, Wen-Kuan Yeh, Hiroyuki Yamauchi, Meng-Fan Chang*, “A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs With Enhanced Read Speed and Cell Stability for IoT Applications,” IEEE Electron Device Letters, Vol. 39. No. 8, pp. 1167-1170, Aug. 2018
Xueqing Li, Sumitha George, Yuhua Liang, Kaisheng Ma, Kai Ni, Ahmedullah Aziz, Sumeet Kumar Gupta, John Sampson, Meng-Fan Chang, Yongpan Liu, Huazhong Yang, Suman Datta, Vijaykrishnan Narayanan, “Lowering Area Overheads for FeFET-Based Energy-Efficient Nonvolatile Flip-Flops,” IEEE Transactions on Electron Devices, Vol. 65, Issue 6, pp. 2670-2674, June 2018
Srivatsa Srinivasa, Xueqing Li, Meng-Fan Chang, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan, “Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 4, pp. 671-683, April 2018
Albert Lee, Hochul Lee, Farbod Ebrahimi,, Bonnie Lam, Wei-Hao Chen, Meng-Fan Chang, Pedram Khalili Amiri, Kang-L. Wang, “A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, pp. 272-279, Feb. 2018
Hsiang-Jen Tsai, Chien-Chih Chen, Yin-Chi Peng, Ya-Han Tsao, Yen-Ning Chiang, Wei-Cheng Zhao, Meng-Fan Chang, Tien-Fu Chen, “A Flexible Wildcard-Pattern Matching Accelerator via Simultaneous Discrete Finite Automata,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25 ,No. 12, pp. 3302-3316, Dec. 2017
Xueqing Li, Sumitha George, Kaisheng Ma, Wei-Yu Tsai, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta, Meng-Fan Chang, Yongpan Liu, Suman Datta, Vijaykrishnan Narayanan, “Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, Issue 11, pp. 2907-2919, Nov. 2017
Xiaoyu Sun, Rui Liu, Yi-Ju Chen, Hsiao-Yun Chiu, Wei-Hao Chen, Meng-Fan Chang, Shimeng Yu, “Low-VDD Operation of SRAM Synaptic Array for Implementing Ternary Neural Network,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Issue 10, pp. 2962-2965, Oct. 2017
Zhibo Wang, Yongpan Liu, Albert Lee, Fang Su, Chieh-Pu Lo, Zhe Yuan, Jinyang Li, Chien-Chen Lin, Wei-Hao Chen, Hsiao-Yun Chiu, Wei-En Lin, Ya-Chin King, Chrong-Jung Lin, Pedram Khalili Amiri, Kang-Lung Wang, Meng-Fan Chang, Huazhong Yang, “A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving >4x Faster Clock Frequency and >6x Higher Restore Speed,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 52, No. 10, pp. 2769-2785, Oct. 2017
Yongpan Liu, ..., Meng-Fan Chang, Huazhong Yang, “Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 36, No. 10, pp. 1660-1673, Oct. 2017
Meng-Fan Chang*, et al., “ A Compact-Area Low-VDDmin 6T SRAM with Improvement in Cell Stability, Read-Speed and Write-Margin Using a Dual-Split-Control Assist Scheme,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 52, No. 9, pp. 2498-2514, Sept. 2017
Albert Lee, C.P. Lo, ……, Meng-Fan Chang*, “A ReRAM-based Nonvolatile Flip-Flop with Self-Write-Termination Scheme for Frequent-Off Fast-Wakeup Nonvolatile Processors ,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 52, No. 8, pp. 2194-2207, Aug. 2017
Xueqing Li, John Sampson, Asif Khan, Kaisheng Ma, Sumitha George, Ahmedullah Aziz, Sumeet Kumar Gupta, Sayeef Salahuddin, Meng-Fan Chang, Suman Datta, Vijaykrishnan Narayanan, “Enabling Energy-Efficient Nonvolatile Computing With Negative Capacitance FET,” IEEE Transactions on Electron Devices, Vol. 64, No. 8, pp. 3452-3458, Aug. 2017
Xueqing Li, Kaisheng Ma, Sumitha George, Win-San Khwa, John Sampson, Sumeet Gupta, Yongpan Liu, Meng-Fan Chang, Suman Datta, Vijaykrishnan Narayanan, “Design of Nonvolatile SRAM with Ferroelectric FETs for Energy-Efficient Backup and Restore,” IEEE Transactions on Electron Devices, Vol. 64, No. 7, pp. 3037-3040, July 2017
Keng-Hao Yang, Hsiang-Jen Tsai, Chia-Yin Li, Paul Jendra, Meng-Fan Chang, Tien-Fu Chen, “eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 64, No. 4, pp. 858-868, April 2017
Hsiang-Jen Tsai, Keng-Hao Yang, Yin-Chi Peng, Chien-Chen Lin, Ya-Han Tsao, Meng-Fan Chang, Tien-Fu Chen, “Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, No. 3, pp. 962-973, March 2017
M.-F. Chang*, et al, “A 3T1R Nonvolatile TCAM using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 52, No. 6, pp. 1664-1679, June 2017
W-S. Khwa, M.-F. Chang, et al., “A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100x for Storage Class Memory Applications,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 52, No. 1, pp. 218-228, Jan. 2017
M.-F. Chang*, L.-Y. Huang, et al, “A ReRAM-Based 4T2R Nonvolatile TCAM Using RC-Filtered Stress-Decoupled Scheme for Frequent-OFF Instant-ON Search Engines Used in IoT and Big-Data Processing,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 11, pp. 2786-2798, Nov. 2016
W-S. Khwa, M.-F. Chang, et al., “A Retention-Aware Multilevel Cell Phase Change Memory Program Evkhwaaluation Metric,” IEEE Electron Device Letters, No. 37, pp. 1422-1425, Nov. 2016
M.-F. Chang*, J.-J. Wu, T.-F. Chien, Y.-C. Liu, T.-C. Yang, W.-C. Shen, Y.-C. King, C.-J. Lin, K.-F. Lin, Y.-D. Chih, and J. Chang, “Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros against Resistance and Switch-Time Variations,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 11, pp. 2786-2795, Nov. 2015
M.-F. Chang*, Y.-F. Lin, Y.-C. Liu, J.-J. Wu, S.-J. Shen, W.-C. Tsai, and Y.-D. Chih, “An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 9, pp. 2188-2198, Sept. 2015
M.-F. Chang*, Albert Lee, P.-C. Chen, C. J. Lin, Y.-C. King, S.-S. Sheu, and T.-K. Ku, “"Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 5, No. 2, pp. 183-193, June 2015
C.-H. Hung, M.-F. Chang*, Y.-S. Yang, Y.-J. Kuo, T.-N. Lai, S.-J. Shen, J.-Y. Hsu, S.-N. Hung, H.-T. Lue, Y.-H. Shih, S.-L. Huang, T.-W. Chen, T.-S. Chen, C. K. Chen, C.-Y. Hung, and C.-Y. Lu, “Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash against Cross-Layer Process Variations,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 6, pp. 1491-1501, June 2015
M.-F. Chang*, S.-M. Yang, C.-C. Kuo, T.-C. Yang, C.-J. Yeh, T.-F. Chien, L.-Y. Huang, S.-S. Sheu, P.-L. Tseng and T.-K. Ku, “Set-Triggered-Parallel-Reset Memristor Logics for High-Density Heterogeneous-Integration Friendly Normally-Off Applications,” IEEE Transactions on Circuits and Systems II, Vol. 62, No. 1, pp. 80-84, Jan. 2015
W. Y. Hsiao, P. C. Peng, T.-S. Chang, Y.-D. Chih, W.-C. Tsai, M.-F. Chang, T.-F. Chien, Y.-C. King, and C.-J. Lin*, “A New High-Density Twin-Gate Isolation One-Time Programmable Memory Cell in Pure 28-nm CMOS Logic Process,” IEEE Transactions on Electron Devices, Vol. 62, No. 1, pp. 121 – 127, Jan. 2015
S.-W. Chiu, J.-H. Wang, K.-H. Chang, T.-H. Chang, C.-M. Wang, C.-L. Chang, C.-T. Tang, C.-F. Chen, C.-H. Shih, H.-W. Kuo, L.-C. Wang, H. Chen, C.-C. Hsieh, M.-F. Chang, Y.-W. Liu, T.-J. Chen, C.-H. Yang, H. M. Chiueh, J.-M. Shyu, K.-T. Tang*, “A Fully Integrated Nose-on-a-Chip for Rapid Diagnosis of Ventilator-Associated Pneumonia,” IEEE Transactions on Biomedical Circuits and Systems, Vol. 8, No. 6, pp. 765-778, June 2014
M.-F. Chang*, C.-C. Kuo, S.-S. Sheu, C.-J. Lin, Y.-C. King, F. T. Chen, T.-K. Ku, M.-J. Tsai, J.-J. Wu, and Y.-D. Chih, “Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 4, pp. 908-916, April 2014
M.-F. Chang*, M.-P. Chen, L.-F. Chen, S.-M. Yang, Y.-J. Kuo, J.-J. Wu, H.-Y. Su, Y.-H. Chu, W.-C. Wu, T.-Y. Yang, and H. Yamauchi, “A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-Vth Read-Port, and Offset Cell VDD Biasing Techniques,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 10, pp. 2558-2569, Oct. 2013
M.-F. Chang*, C.-W. Wu, C.-C. Kuo, S.-J. Shen, S.-M. Yang, K.-F. Lin, W.-C. Shen, Y.-C. King, C.-J. Lin, and Y.-D. Chih, “A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5V 4Mb 65nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 9, pp. 2250-2259, Sept. 2013
M.-F. Chang*, et al., “A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 6, pp. 1521-1529, June 2013
W.-T. Chen, Y.-L. Lin, C.-Y. Lee, J.-L. Chiang, M.-F. Chang, and S.-C. Chang*, “Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan,” IEEE Access, Vol. 1, pp. 123-130, June 2013
M.-F. Chang*, et al., “A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 3, pp. 878-891, March 2013
M.-F. Chang*, et al., “An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 3, pp. 864-877, March 2013
S.-M. Yang, M.-F. Chang*, et al., “Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for Speed and Power Improvement,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 2, pp. 611-623, Feb. 2013
J.-J. Wu, M.-F. Chang*, S.-W. Lu, R. Lo, and Q. Li, “A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances,” IEEE Transactions on Circuits and Systems II, Vol. 59, No. 11, pp. 790-794, Nov. 2012
P.-F. Chiu, M. F. Chang*, C.-W. Wu, C.-H. Chuang, S.-S. Sheu, Y.-S. Chen, and M.-J. Tsai, “Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM with Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 47, No. 6, pp. 1483-1496 , June 2012
Y.-H. Chen, S.-Y. Chou, Q. Li, W.-M. Chan, D. Sun, H.-J. Liao, P. Wang, M.-F. Chang*, and H. Yamauchi, “Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in A 40nm Fully Functional Embedded SRAM,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 47, No. 4, pp. 969-980, April 2012
C.-H. Wang, Y.-H. Tsai, K.-C. Lin, M.-F. Chang, Y.-C. King, C. J. Lin*, et al., “Three-Dimensional 4F2 ReRAM with Vertical BJT Driver by CMOS Logic Compatible Process,” IEEE Transactions on Electron Devices, Vol. 58, No. 8, pp. 2466-2472, Aug. 2011
K.-T. Tang*, S.-W. Chiu, M.-F. Chang, C.-C. Hsieh and J.-M. Shyu, “A Low-Power Electronic Nose Signal-Processing Chip for a Portable Artificial Olfaction System,” IEEE Transactions on Biomedical Circuits and Systems, Vol. 5, No. 4, pp. 380-390, Aug. 2011
J.-J. Wu, Y.-H. Chen, M.-F. Chang*, P.-W. Chou, C.-Y. Chen, H.-J. Liao, M.-B. Chen, Y.-H. Chu, W.-C. Wu, and H. Yamauchi, “A Large σVTH/VDD Tolerant Zigzag 8T SRAM with Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 4, pp. 815-827, April 2011
M.-F. Chang*, S.-W. Chang, P.-W. Chou and W.-C. Wu, “A 130mV SRAM with Expanded Write and Read Margins for Subthreshold Applications,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 2, pp. 520-529, Feb. 2011
S.-S. Sheu*, K.-H. Cheng, M.-F. Chang, et al., “Fast Access Speed RRAM for Embedded Applications,” IEEE Design and Test of Computers, Vol. 28. No. 1, pp. 64-71, Jan. 2011
M.-F. Chang*, Y.-C. Chen and C.-F. Chen, “A 0.45V 300MHz 10T Flow-Through SRAM with Expanded Write/Read Stability and Speed-Area-Wise Array for sub-0.5V Chips,” IEEE Transactions on Circuits and Systems II, Vol. 57, No. 12, pp. 980-985, Dec. 2010
M.-F. Chang*, S.-M. Yang, C.-W. Liang, C.-C. Chiang, P.-F. Chiu, and K.-F. Lin, “Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-line Scheme for VDDmin and Speed Improvements,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 45, No. 10, pp. 2142-2155, Oct. 2010
M.-F. Chang*, J.-J. Wu, K.-T. Chen, Y.-C. Chen, Y.-H. Chen, R. Lee, H.-J. Liao and H. Yamauchi, “A Differential Data Aware Power-supplied (D2AP) 8T SRAM Cell with Expanded Write/Read Stabilities for Lower VDDmin Applications,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 45, No. 6, pp. 1234-1245, June 2010
M.-F. Chang* and S.-J. Shen, “A process variation tolerant embedded split-gate Flash memory using pre-stable current sensing scheme,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 44, No. 3, pp. 987-994, March 2009 (SCI)
M.-F. Chang*, S.-M. Yang, and K.-T. Chen, “Wide-VDD embedded asynchronous SRAM with dual-mode self-timed technique for dynamic voltage systems,” IEEE Transactions on Circuits and Systems I, Vol. 56, No. 8 pp. 1657-1667, Aug. 2009 (SCI)
M.-F. Chang* and S.-M. Yang, “Analysis and reduction of supply noise fluctuations induced by embedded ROM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 17, No. 6, pp. 758-769, June 2009 (SCI)
M.-F. Chang*, L.-Y. Chiou, and K.-A. Wen, “Crosstalk-insensitive via-programming ROMs using content-aware design framework,” IEEE Transactions on Circuits and Systems II, Vol. 53, Issue 6, pp. 443-447, June 2006 (SCI)
M.-F. Chang*, L.-Y. Chiou, and K.-A. Wen, “A full code-pattern coverage high-speed embedded ROM using dynamic virtual guardian technique,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 41, No. 2, pp. 496-506, Feb. 2006 (SCI)
M.-F. Chang*, L.-Y. Chiou, and K.-A. Wen, “Code-pattern insensitive embedded ROMs using dynamic bitline shielding technique,” IEE Electronics Letters, Vol. 41, No. 15, pp. 834-835, July 2005 (SCI)
M.-F. Chang* and K.-A. Wen, “Power and substrate noise tolerance of configurable embedded memories in SoC,” Journal of VLSI Signal Processing Systems, Special Issue on System-on-a-Chip, Vol. 41, No. 1, pp. 81-91, Aug. 2005 (EI)
M.-F. Chang, M. J. Irwin*, and R. M. Owens, “Power-area tradeoff in dual word line memory cell arrays,” Journal of Circuits, Systems and Computers, Vol. 7, No. 1, pp. 49–67, Feb. 1997 (EI)